Message ID | 20231025135001.531224-5-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | RVA22U64 profile support | expand |
On Wed, Oct 25, 2023 at 10:49:56AM -0300, Daniel Henrique Barboza wrote: > We already track user choice for multi-letter extensions because we > needed to honor user choice when enabling/disabling extensions during > realize(). We refrained from adding the same mechanism for MISA > extensions since we didn't need it. > > Profile support requires tne need to check for user choice for MISA > extensions, so let's add the corresponding hash now. It works like the > existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits > options in the cpu_set_misa_ext_cfg() callback. > > Note that we can't re-use the same hash from multi-letter extensions > because that hash uses cpu->cfg offsets as keys, while for MISA > extensions we're using MISA bits as keys. > > After adding the user hash in cpu_set_misa_ext_cfg(), setting default > values with object_property_set_bool() in add_misa_properties() will end > up marking the user choice hash with them. Set the default value > manually to avoid it. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > --- > target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 572ae9c902..f3fc318704 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -34,6 +34,7 @@ /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; +static GHashTable *misa_ext_user_opts; static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { @@ -681,6 +682,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, return; } + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit), + (gpointer)value); + prev_val = env->misa_ext & misa_bit; if (value == prev_val) { @@ -744,6 +749,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + CPURISCVState *env = &RISCV_CPU(cpu_obj)->env; bool use_def_vals = riscv_cpu_is_generic(cpu_obj); int i; @@ -764,7 +770,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + if (misa_cfg->enabled) { + env->misa_ext |= bit; + env->misa_ext_mask |= bit; + } else { + env->misa_ext &= ~bit; + env->misa_ext_mask &= ~bit; + } } } } @@ -995,6 +1007,7 @@ static void tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); Object *obj = OBJECT(cpu); + misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj);