Message ID | 20231020223951.357513-2-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | riscv: RVA22U64 profile support | expand |
On 2023/10/21 6:39, Daniel Henrique Barboza wrote: > The rva22U64 profile, described in: > > https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles > > Contains a set of CPU extensions aimed for 64-bit userspace > applications. Enabling this set to be enabled via a single user flag > makes it convenient to enable a predictable set of features for the CPU, > giving users more predicability when running/testing their workloads. > > QEMU implements all possible extensions of this profile. The exception > is Zicbop (Cache-Block Prefetch Operations) that is not available since > QEMU RISC-V does not implement a cache model. For this same reason all > the so called 'synthetic extensions' described in the profile that are > cache related are ignored (Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa, > Zicclsm). > > An abstraction called RISCVCPUProfile is created to store the profile. > 'ext_offsets' contains mandatory extensions that QEMU supports. Same > thing with the 'misa_ext' mask. Optional extensions must be enabled > manually in the command line if desired. > > The design here is to use the common target/riscv/cpu.c file to store > the profile declaration and export it to the accelerator files. Each > accelerator is then responsible to expose it (or not) to users and how > to enable the extensions. > > Next patches will implement the profile for TCG and KVM. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Acked-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 20 ++++++++++++++++++++ > target/riscv/cpu.h | 12 ++++++++++++ > 2 files changed, 32 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c64cd726f4..1b75b506c4 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1397,6 +1397,26 @@ Property riscv_cpu_options[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > +/* Optional extensions left out: RVV, zfh, zkn, zks */ > +static RISCVCPUProfile RVA22U64 = { > + .name = "rva22u64", > + .misa_ext = RVM | RVA | RVF | RVD | RVC, Why not include RVI? Zhiwei > + .ext_offsets = { > + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), > + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), > + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), > + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), > + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), > + CPU_CFG_OFFSET(ext_zicboz), > + > + RISCV_PROFILE_EXT_LIST_END > + } > +}; > + > +RISCVCPUProfile *riscv_profiles[] = { > + &RVA22U64, NULL, > +}; > + > static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 7f61e17202..53c1970e0a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -66,6 +66,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit); > > #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) > > +typedef struct riscv_cpu_profile { > + const char *name; > + uint32_t misa_ext; > + bool enabled; > + bool user_set; > + const int32_t ext_offsets[]; > +} RISCVCPUProfile; > + > +#define RISCV_PROFILE_EXT_LIST_END -1 > + > +extern RISCVCPUProfile *riscv_profiles[]; > + > /* Privileged specification version */ > enum { > PRIV_VERSION_1_10_0 = 0,
On 10/25/23 03:22, LIU Zhiwei wrote: > > On 2023/10/21 6:39, Daniel Henrique Barboza wrote: >> The rva22U64 profile, described in: >> >> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles >> >> Contains a set of CPU extensions aimed for 64-bit userspace >> applications. Enabling this set to be enabled via a single user flag >> makes it convenient to enable a predictable set of features for the CPU, >> giving users more predicability when running/testing their workloads. >> >> QEMU implements all possible extensions of this profile. The exception >> is Zicbop (Cache-Block Prefetch Operations) that is not available since >> QEMU RISC-V does not implement a cache model. For this same reason all >> the so called 'synthetic extensions' described in the profile that are >> cache related are ignored (Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa, >> Zicclsm). >> >> An abstraction called RISCVCPUProfile is created to store the profile. >> 'ext_offsets' contains mandatory extensions that QEMU supports. Same >> thing with the 'misa_ext' mask. Optional extensions must be enabled >> manually in the command line if desired. >> >> The design here is to use the common target/riscv/cpu.c file to store >> the profile declaration and export it to the accelerator files. Each >> accelerator is then responsible to expose it (or not) to users and how >> to enable the extensions. >> >> Next patches will implement the profile for TCG and KVM. >> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> Acked-by: Alistair Francis <alistair.francis@wdc.com> >> --- >> target/riscv/cpu.c | 20 ++++++++++++++++++++ >> target/riscv/cpu.h | 12 ++++++++++++ >> 2 files changed, 32 insertions(+) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index c64cd726f4..1b75b506c4 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -1397,6 +1397,26 @@ Property riscv_cpu_options[] = { >> DEFINE_PROP_END_OF_LIST(), >> }; >> +/* Optional extensions left out: RVV, zfh, zkn, zks */ >> +static RISCVCPUProfile RVA22U64 = { >> + .name = "rva22u64", >> + .misa_ext = RVM | RVA | RVF | RVD | RVC, > > Why not include RVI? Because I forgot :D I'll fix it in v4. Thanks, Daniel > > Zhiwei > >> + .ext_offsets = { >> + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), >> + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), >> + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), >> + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), >> + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), >> + CPU_CFG_OFFSET(ext_zicboz), >> + >> + RISCV_PROFILE_EXT_LIST_END >> + } >> +}; >> + >> +RISCVCPUProfile *riscv_profiles[] = { >> + &RVA22U64, NULL, >> +}; >> + >> static Property riscv_cpu_properties[] = { >> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index 7f61e17202..53c1970e0a 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -66,6 +66,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit); >> #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) >> +typedef struct riscv_cpu_profile { >> + const char *name; >> + uint32_t misa_ext; >> + bool enabled; >> + bool user_set; >> + const int32_t ext_offsets[]; >> +} RISCVCPUProfile; >> + >> +#define RISCV_PROFILE_EXT_LIST_END -1 >> + >> +extern RISCVCPUProfile *riscv_profiles[]; >> + >> /* Privileged specification version */ >> enum { >> PRIV_VERSION_1_10_0 = 0,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c64cd726f4..1b75b506c4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1397,6 +1397,26 @@ Property riscv_cpu_options[] = { DEFINE_PROP_END_OF_LIST(), }; +/* Optional extensions left out: RVV, zfh, zkn, zks */ +static RISCVCPUProfile RVA22U64 = { + .name = "rva22u64", + .misa_ext = RVM | RVA | RVF | RVD | RVC, + .ext_offsets = { + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), + CPU_CFG_OFFSET(ext_zicboz), + + RISCV_PROFILE_EXT_LIST_END + } +}; + +RISCVCPUProfile *riscv_profiles[] = { + &RVA22U64, NULL, +}; + static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7f61e17202..53c1970e0a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit); #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) +typedef struct riscv_cpu_profile { + const char *name; + uint32_t misa_ext; + bool enabled; + bool user_set; + const int32_t ext_offsets[]; +} RISCVCPUProfile; + +#define RISCV_PROFILE_EXT_LIST_END -1 + +extern RISCVCPUProfile *riscv_profiles[]; + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 = 0,