| Message ID | 20231020223951.357513-7-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: RVA22U64 profile support | expand |
On 2023/10/21 6:39, Daniel Henrique Barboza wrote: > The profile support is handling multi-letter extensions only. Let's add > support for MISA bits as well. > > We'll go through every known MISA bit. If the user set the bit, doesn't > matter if to 'true' or 'false', ignore it. If the profile doesn't > declare the bit as mandatory, ignore it. Otherwise, set or clear the bit > in env->misa_ext and env->misa_ext_mask depending on whether the profile > was set to 'true' or 'false'. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/tcg/tcg-cpu.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index ba11d0566d..73c7453af6 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -42,6 +42,12 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) > GUINT_TO_POINTER(ext_offset)); > } > > +static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) > +{ > + return g_hash_table_contains(misa_ext_user_opts, > + GUINT_TO_POINTER(misa_bit)); > +} > + > static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, > bool enabled) > { > @@ -797,6 +803,16 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, > > profile->enabled = value; > > + for (i = 0; misa_bits[i] != 0; i++) { > + uint32_t bit = misa_bits[i]; > + > + if (cpu_misa_ext_is_user_set(bit) || !(profile->misa_ext & bit)) { > + continue; > + } > + > + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); > + } > + Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { > ext_offset = profile->ext_offsets[i]; >
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ba11d0566d..73c7453af6 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,12 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } +static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) +{ + return g_hash_table_contains(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit)); +} + static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, bool enabled) { @@ -797,6 +803,16 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, profile->enabled = value; + for (i = 0; misa_bits[i] != 0; i++) { + uint32_t bit = misa_bits[i]; + + if (cpu_misa_ext_is_user_set(bit) || !(profile->misa_ext & bit)) { + continue; + } + + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); + } + for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { ext_offset = profile->ext_offsets[i];
The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the user set the bit, doesn't matter if to 'true' or 'false', ignore it. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set or clear the bit in env->misa_ext and env->misa_ext_mask depending on whether the profile was set to 'true' or 'false'. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/tcg/tcg-cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)