[risu,v2,1/4] s390x: Add basic s390x support to the C code

diff --git a/risu_reginfo_s390x.c b/risu_reginfo_s390x.c
new file mode 100644
index 0000000..1c6aa0c
--- /dev/null
+++ b/risu_reginfo_s390x.c
@@ -0,0 +1,140 @@ 
+/******************************************************************************
+ * Copyright 2023 Red Hat Inc.
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ *     Thomas Huth - initial implementation
+ *****************************************************************************/
+
+#include <stdio.h>
+#include <ucontext.h>
+#include <string.h>
+#include <math.h>
+#include <stdlib.h>
+#include <sys/user.h>
+
+#include "risu.h"
+#include "risu_reginfo_s390x.h"
+
+
+const struct option * const arch_long_opts;
+const char * const arch_extra_help;
+
+void process_arch_opt(int opt, const char *arg)
+{
+    abort();
+}
+
+void arch_init(void)
+{
+}
+
+int reginfo_size(struct reginfo *ri)
+{
+    return sizeof(*ri);
+}
+
+/* reginfo_init: initialize with a ucontext */
+void reginfo_init(struct reginfo *ri, ucontext_t *uc)
+{
+    int i;
+
+    memset(ri, 0, sizeof(*ri));
+
+    ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.psw.addr);
+    ri->psw_mask = uc->uc_mcontext.psw.mask;
+    ri->psw_addr = uc->uc_mcontext.psw.addr - image_start_address;
+
+    for (i = 0; i < 16; i++) {
+        ri->gregs[i] = uc->uc_mcontext.gregs[i];
+    }
+
+    memcpy(&ri->fpregs, &uc->uc_mcontext.fpregs, sizeof(fpregset_t));
+}
+
+/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
+int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
+{
+    int i;
+
+    if (m->psw_mask != a->psw_mask || m->psw_addr != a->psw_addr) {
+        return 0;
+    }
+
+    for (i = 0; i < 16; i++) {
+        if (m->gregs[i] != a->gregs[i]) {
+            return 0;
+        }
+    }
+
+    if (memcmp(&m->fpregs, &a->fpregs, sizeof(fpregset_t))) {
+        return 0;
+    }
+
+    return 1;
+}
+
+/* reginfo_dump: print state to a stream, returns nonzero on success */
+int reginfo_dump(struct reginfo *ri, FILE * f)
+{
+    int i;
+
+    fprintf(f, "  faulting insn 0x%x\n", ri->faulting_insn);
+    fprintf(f, "  PSW mask      0x%" PRIx64 "\n", ri->psw_mask);
+    fprintf(f, "  PSW addr offs 0x%" PRIx64 "\n\n", ri->psw_addr);
+
+    for (i = 0; i < 16/2; i++) {
+        fprintf(f, "\tr%d: %16lx\tr%02d: %16lx\n", i, ri->gregs[i],
+                i + 8, ri->gregs[i + 8]);
+    }
+    fprintf(f, "\n");
+
+    for (i = 0; i < 16/2; i++) {
+        fprintf(f, "\tf%d: %16lx\tf%02d: %16lx\n",
+                i, *(uint64_t *)&ri->fpregs.fprs[i],
+                i + 8, *(uint64_t *)&ri->fpregs.fprs[i + 8]);
+    }
+    fprintf(f, "\tFPC: %8x\n\n", ri->fpregs.fpc);
+
+    return !ferror(f);
+}
+
+int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
+{
+    int i;
+
+    if (m->psw_mask != a->psw_mask) {
+        fprintf(f, "Mismatch: PSW mask master: [%016lx] - PSW mask apprentice: [%016lx]\n",
+                m->psw_mask, a->psw_mask);
+    }
+
+    if (m->psw_addr != a->psw_addr) {
+        fprintf(f, "Mismatch: PSW addr offset master: [%016lx] - PSW addr offset apprentice: [%016lx]\n",
+                m->psw_addr, a->psw_addr);
+    }
+
+    for (i = 0; i < 16; i++) {
+        if (m->gregs[i] != a->gregs[i]) {
+            fprintf(f, "Mismatch: r%d master: [%016lx] - r%d apprentice: [%016lx]\n",
+                    i, m->gregs[i], i, a->gregs[i]);
+        }
+    }
+
+    for (i = 0; i < 16; i++) {
+        if (*(uint64_t *)&m->fpregs.fprs[i] != *(uint64_t *)&a->fpregs.fprs[i]) {
+            fprintf(f, "Mismatch: f%d master: [%016lx] - f%d apprentice: [%016lx]\n",
+                    i, *(uint64_t *)&m->fpregs.fprs[i],
+                    i, *(uint64_t *)&a->fpregs.fprs[i]);
+        }
+    }
+
+    if (m->fpregs.fpc != a->fpregs.fpc) {
+        fprintf(f, "Mismatch: FPC master: [%08x] - FPC apprentice: [%08x]\n",
+                m->fpregs.fpc, a->fpregs.fpc);
+    }
+
+    return !ferror(f);
+}
diff --git a/risu_reginfo_s390x.h b/risu_reginfo_s390x.h
new file mode 100644
index 0000000..b55a11d
--- /dev/null
+++ b/risu_reginfo_s390x.h
@@ -0,0 +1,23 @@ 
+/******************************************************************************
+ * Copyright 2023 Red Hat Inc.
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ *     Thomas Huth - initial implementation
+ *****************************************************************************/
+
+#ifndef RISU_REGINFO_S390X_H
+#define RISU_REGINFO_S390X_H
+
+struct reginfo {
+    uint32_t faulting_insn;
+    uint64_t psw_mask;
+    uint64_t psw_addr;
+    gregset_t gregs;
+    fpregset_t fpregs;
+};
+
+#endif /* RISU_REGINFO_S390X_H */
diff --git a/risu_s390x.c b/risu_s390x.c
new file mode 100644
index 0000000..4a83869
--- /dev/null
+++ b/risu_s390x.c
@@ -0,0 +1,48 @@ 
+/******************************************************************************
+ * Copyright 2023 Red Hat Inc.
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ *     Thomas Huth - initial implementation
+ *****************************************************************************/
+
+#include <sys/user.h>
+
+#include "risu.h"
+
+void advance_pc(void *vuc)
+{
+    /*
+     * Note: The PSW address already points to the next instruction
+     * after we get a SIGILL, so we must not advance it here!
+     */
+    // ucontext_t *uc = (ucontext_t *) vuc;
+    // uc->uc_mcontext.psw.addr += 4;
+}
+
+void set_ucontext_paramreg(void *vuc, uint64_t value)
+{
+    ucontext_t *uc = vuc;
+    uc->uc_mcontext.gregs[0] = value;
+}
+
+uint64_t get_reginfo_paramreg(struct reginfo *ri)
+{
+    return ri->gregs[0];
+}
+
+RisuOp get_risuop(struct reginfo *ri)
+{
+    uint32_t insn = ri->faulting_insn;
+    uint32_t op = insn & 0xff;
+    uint32_t key = insn & ~0xff;
+    return (key != 0x835a0f00) ? OP_SIGILL : op;
+}
+
+uintptr_t get_pc(struct reginfo *ri)
+{
+   return ri->psw_addr;
+}
diff --git a/test_s390x.S b/test_s390x.S
new file mode 100644
index 0000000..59f365f
--- /dev/null
+++ b/test_s390x.S
@@ -0,0 +1,51 @@ 
+/*****************************************************************************
+ * Copyright 2023 Red Hat Inc.
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ *     Thomas Huth - initial implementation
+ *****************************************************************************/
+
+    /* Initialise the general purpose registers */
+    lgfi %r0, 0
+    lgfi %r1, 0x1111111
+    lgfi %r2, 0x2222222
+    lgfi %r3, 0x3333333
+    lgfi %r4, 0x4444444
+    lgfi %r5, 0x5555555
+    lgfi %r6, 0x6666666
+    lgfi %r7, 0x7777777
+    lgfi %r8, 0x8888888
+    lgfi %r9, 0x9999999
+    lgfi %r10, 0xaaaaaaa
+    lgfi %r11, 0xbbbbbbb
+    lgfi %r12, 0xccccccc
+    lgfi %r13, 0xddddddd
+    lgfi %r14, 0xeeeeeee
+    lgfi %r15, 0xfffffff
+
+    /* Initialize floating point registers */
+    ldgr %f0,%r0
+    ldgr %f1,%r1
+    ldgr %f2,%r2
+    ldgr %f3,%r3
+    ldgr %f4,%r4
+    ldgr %f5,%r5
+    ldgr %f6,%r6
+    ldgr %f7,%r7
+    ldgr %f8,%r8
+    ldgr %f9,%r9
+    ldgr %f10,%r10
+    ldgr %f11,%r11
+    ldgr %f12,%r12
+    ldgr %f13,%r13
+    ldgr %f14,%r14
+    ldgr %f15,%r15
+
+    /* do compare */
+    .int 0x835a0f00
+    /* exit test */
+    .int 0x835a0f01