Message ID | 20230907083158.3975132-52-gaosong@loongson.cn |
---|---|
State | New |
Headers | show |
Series | Add LoongArch LASX instructions | expand |
On 9/7/23 01:31, Song Gao wrote: > +static bool trans_xvinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) > +{ > + if (!avail_LASX(ctx)) { > + return false; > + } > + return trans_vinsgr2vr_w(ctx, a); > +} Using the other translator doesn't help. > static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) > { > TCGv src = gpr_src(ctx, a->rj, EXT_NONE); > > if (!avail_LSX(ctx)) { > return false; > } > > CHECK_SXE; This portion doesn't apply, and you miss the check_vec for the larger LASX. > tcg_gen_st32_i64(src, cpu_env, > offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm))); > return true; > } The only thing that is left is this one line, so I'm not sure it's worth splitting out a common helper function. r~
在 2023/9/12 上午6:27, Richard Henderson 写道: > On 9/7/23 01:31, Song Gao wrote: >> +static bool trans_xvinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) >> +{ >> + if (!avail_LASX(ctx)) { >> + return false; >> + } >> + return trans_vinsgr2vr_w(ctx, a); >> +} > > Using the other translator doesn't help. > >> static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) >> { >> TCGv src = gpr_src(ctx, a->rj, EXT_NONE); >> >> if (!avail_LSX(ctx)) { >> return false; >> } >> >> CHECK_SXE; > > This portion doesn't apply, and you miss the check_vec for the larger LASX. > >> tcg_gen_st32_i64(src, cpu_env, >> offsetof(CPULoongArchState, >> fpr[a->vd].vreg.W(a->imm))); >> return true; >> } > > The only thing that is left is this one line, so I'm not sure it's worth > splitting out a common helper function. > > I think we need, like this: static bool gen_g2v_vl(DisasContext *ctx, arg_vr_i *a, uint32_t oprsz, MemOp mop, void (*func)(TCGv, TCGv_ptr, tcg_target_long)) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); if (!check_vec(ctx, oprsz)) { return true; } func(src, cpu_env, vec_reg_offset(a->vd, a->imm, mop)); return true; } static bool gen_g2v(DisasContext *ctx, arg_vr_i *a, MemOp mop, void (*func)(TCGv, TCGv_ptr, tcg_target_long)) { return gen_g2v_vl(ctx, a, 16, mop, func); } static bool gen_g2x(DisasContext *ctx, arg_vr_i *a, MemOp mop, void (*func)(TCGv, TCGv_ptr, tcg_target_long)) { return gen_g2v_vl(ctx, a, 32, mop, func); } TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_i64) TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_i64) TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_i64) TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_i64) TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_i64) TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_i64) Thanks. Song Gao
On 9/12/23 02:09, gaosong wrote: > static bool gen_g2v_vl(DisasContext *ctx, arg_vr_i *a, uint32_t oprsz, MemOp mop, > void (*func)(TCGv, TCGv_ptr, tcg_target_long)) > { > TCGv src = gpr_src(ctx, a->rj, EXT_NONE); > > if (!check_vec(ctx, oprsz)) { > return true; > } > > func(src, cpu_env, vec_reg_offset(a->vd, a->imm, mop)); > > return true; > } > > static bool gen_g2v(DisasContext *ctx, arg_vr_i *a, MemOp mop, > void (*func)(TCGv, TCGv_ptr, tcg_target_long)) > { > return gen_g2v_vl(ctx, a, 16, mop, func); > } > > static bool gen_g2x(DisasContext *ctx, arg_vr_i *a, MemOp mop, > void (*func)(TCGv, TCGv_ptr, tcg_target_long)) > { > return gen_g2v_vl(ctx, a, 32, mop, func); > } > > TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_i64) > TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_i64) > TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_i64) > TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_i64) > TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_i64) > TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_i64) Looks perfect, thanks. r~
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index ad6751fdfb..bb3bb447ae 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1976,6 +1976,13 @@ xvsetallnez_h 0111 01101001 11001 01101 ..... 00 ... @cv xvsetallnez_w 0111 01101001 11001 01110 ..... 00 ... @cv xvsetallnez_d 0111 01101001 11001 01111 ..... 00 ... @cv +xvinsgr2vr_w 0111 01101110 10111 10 ... ..... ..... @vr_ui3 +xvinsgr2vr_d 0111 01101110 10111 110 .. ..... ..... @vr_ui2 +xvpickve2gr_w 0111 01101110 11111 10 ... ..... ..... @rv_ui3 +xvpickve2gr_d 0111 01101110 11111 110 .. ..... ..... @rv_ui2 +xvpickve2gr_wu 0111 01101111 00111 10 ... ..... ..... @rv_ui3 +xvpickve2gr_du 0111 01101111 00111 110 .. ..... ..... @rv_ui2 + xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index abe113b150..04f9f9fa4b 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1738,6 +1738,16 @@ static void output_vv_x(DisasContext *ctx, arg_vv *a, const char *mnemonic) output(ctx, mnemonic, "x%d, x%d", a->vd, a->vj); } +static void output_vr_i_x(DisasContext *ctx, arg_vr_i *a, const char *mnemonic) +{ + output(ctx, mnemonic, "x%d, r%d, 0x%x", a->vd, a->rj, a->imm); +} + +static void output_rv_i_x(DisasContext *ctx, arg_rv_i *a, const char *mnemonic) +{ + output(ctx, mnemonic, "r%d, x%d, 0x%x", a->rd, a->vj, a->imm); +} + INSN_LASX(xvadd_b, vvv) INSN_LASX(xvadd_h, vvv) INSN_LASX(xvadd_w, vvv) @@ -2497,6 +2507,13 @@ INSN_LASX(xvsetallnez_h, cv) INSN_LASX(xvsetallnez_w, cv) INSN_LASX(xvsetallnez_d, cv) +INSN_LASX(xvinsgr2vr_w, vr_i) +INSN_LASX(xvinsgr2vr_d, vr_i) +INSN_LASX(xvpickve2gr_w, rv_i) +INSN_LASX(xvpickve2gr_d, rv_i) +INSN_LASX(xvpickve2gr_wu, rv_i) +INSN_LASX(xvpickve2gr_du, rv_i) + INSN_LASX(xvreplgr2vr_b, vr) INSN_LASX(xvreplgr2vr_h, vr) INSN_LASX(xvreplgr2vr_w, vr) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc index b68daa53ae..bf44a4d1fc 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -5268,6 +5268,54 @@ static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a) return true; } +static bool trans_xvinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) +{ + if (!avail_LASX(ctx)) { + return false; + } + return trans_vinsgr2vr_w(ctx, a); +} + +static bool trans_xvinsgr2vr_d(DisasContext *ctx, arg_vr_i *a) +{ + if (!avail_LASX(ctx)) { + return false; + } + return trans_vinsgr2vr_d(ctx, a); +} + +static bool trans_xvpickve2gr_w(DisasContext *ctx, arg_rv_i *a) +{ + if (!avail_LASX(ctx)) { + return false; + } + return trans_vpickve2gr_w(ctx, a); +} + +static bool trans_xvpickve2gr_d(DisasContext *ctx, arg_rv_i *a) +{ + if (!avail_LASX(ctx)) { + return false; + } + return trans_vpickve2gr_d(ctx, a); +} + +static bool trans_xvpickve2gr_wu(DisasContext *ctx, arg_rv_i *a) +{ + if (!avail_LASX(ctx)) { + return false; + } + return trans_vpickve2gr_wu(ctx, a); +} + +static bool trans_xvpickve2gr_du(DisasContext *ctx, arg_rv_i *a) +{ + if (!avail_LASX(ctx)) { + return false; + } + return trans_vpickve2gr_du(ctx, a); +} + static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a, uint32_t oprsz, MemOp mop) {
This patch includes: - XVINSGR2VR.{W/D}; - XVPICKVE2GR.{W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> --- target/loongarch/insns.decode | 7 +++ target/loongarch/disas.c | 17 ++++++++ target/loongarch/insn_trans/trans_vec.c.inc | 48 +++++++++++++++++++++ 3 files changed, 72 insertions(+)