| Message ID | 20230825130853.511782-17-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: split TCG/KVM accelerators from cpu.c | expand |
On Fri, Aug 25, 2023 at 10:08:49AM -0300, Daniel Henrique Barboza wrote: > All code related to MISA TCG properties is also moved. > > At this point, all TCG properties handling is done in tcg-cpu.c, all KVM > properties handling is done in kvm-cpu.c. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.c | 89 -------------------------------------- > target/riscv/cpu.h | 1 - > target/riscv/tcg/tcg-cpu.c | 84 +++++++++++++++++++++++++++++++++++ > 3 files changed, 84 insertions(+), 90 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 89b09a7e89..3c9db46837 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1201,49 +1201,6 @@ static void riscv_cpu_init(Object *obj) > #endif /* CONFIG_USER_ONLY */ > } > > -typedef struct RISCVCPUMisaExtConfig { > - const char *name; > - const char *description; > - target_ulong misa_bit; > - bool enabled; > -} RISCVCPUMisaExtConfig; > - > -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, > - void *opaque, Error **errp) > -{ > - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; > - target_ulong misa_bit = misa_ext_cfg->misa_bit; > - RISCVCPU *cpu = RISCV_CPU(obj); > - CPURISCVState *env = &cpu->env; > - bool value; > - > - if (!visit_type_bool(v, name, &value, errp)) { > - return; > - } > - > - if (value) { > - env->misa_ext |= misa_bit; > - env->misa_ext_mask |= misa_bit; > - } else { > - env->misa_ext &= ~misa_bit; > - env->misa_ext_mask &= ~misa_bit; > - } > -} > - > -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, > - void *opaque, Error **errp) > -{ > - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; > - target_ulong misa_bit = misa_ext_cfg->misa_bit; > - RISCVCPU *cpu = RISCV_CPU(obj); > - CPURISCVState *env = &cpu->env; > - bool value; > - > - value = env->misa_ext & misa_bit; > - > - visit_type_bool(v, name, &value, errp); > -} > - > typedef struct misa_ext_info { > const char *name; > const char *description; > @@ -1304,52 +1261,6 @@ const char *riscv_get_misa_ext_description(uint32_t bit) > return val; > } > > -#define MISA_CFG(_bit, _enabled) \ > - {.misa_bit = _bit, .enabled = _enabled} > - > -static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > - MISA_CFG(RVA, true), > - MISA_CFG(RVC, true), > - MISA_CFG(RVD, true), > - MISA_CFG(RVF, true), > - MISA_CFG(RVI, true), > - MISA_CFG(RVE, false), > - MISA_CFG(RVM, true), > - MISA_CFG(RVS, true), > - MISA_CFG(RVU, true), > - MISA_CFG(RVH, true), > - MISA_CFG(RVJ, false), > - MISA_CFG(RVV, false), > - MISA_CFG(RVG, false), > -}; > - > -void riscv_cpu_add_misa_properties(Object *cpu_obj) > -{ > - int i; > - > - for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { > - RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; > - int bit = misa_cfg->misa_bit; > - > - misa_cfg->name = riscv_get_misa_ext_name(bit); > - misa_cfg->description = riscv_get_misa_ext_description(bit); > - > - /* Check if KVM already created the property */ > - if (object_property_find(cpu_obj, misa_cfg->name)) { > - continue; > - } > - > - object_property_add(cpu_obj, misa_cfg->name, "bool", > - cpu_get_misa_ext_cfg, > - cpu_set_misa_ext_cfg, > - NULL, (void *)misa_cfg); > - object_property_set_description(cpu_obj, misa_cfg->name, > - misa_cfg->description); > - object_property_set_bool(cpu_obj, misa_cfg->name, > - misa_cfg->enabled, NULL); > - } > -} > - > #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ > {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ > .enabled = _defval} > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 74fbb33e09..4269523e24 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; > extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; > extern Property riscv_cpu_options[]; > > -void riscv_cpu_add_misa_properties(Object *cpu_obj); > void riscv_add_satp_mode_properties(Object *obj); > > /* CSR function table */ > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 68ce3cbcb9..8e3f55d3a6 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -574,6 +574,90 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) > return true; > } > > +typedef struct RISCVCPUMisaExtConfig { > + const char *name; > + const char *description; > + target_ulong misa_bit; > + bool enabled; > +} RISCVCPUMisaExtConfig; > + > +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; > + target_ulong misa_bit = misa_ext_cfg->misa_bit; > + RISCVCPU *cpu = RISCV_CPU(obj); > + CPURISCVState *env = &cpu->env; > + bool value; > + > + if (!visit_type_bool(v, name, &value, errp)) { > + return; > + } > + > + if (value) { > + env->misa_ext |= misa_bit; > + env->misa_ext_mask |= misa_bit; > + } else { > + env->misa_ext &= ~misa_bit; > + env->misa_ext_mask &= ~misa_bit; > + } > +} > + > +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; > + target_ulong misa_bit = misa_ext_cfg->misa_bit; > + RISCVCPU *cpu = RISCV_CPU(obj); > + CPURISCVState *env = &cpu->env; > + bool value; > + > + value = env->misa_ext & misa_bit; > + > + visit_type_bool(v, name, &value, errp); > +} > + > +#define MISA_CFG(_bit, _enabled) \ > + {.misa_bit = _bit, .enabled = _enabled} > + > +static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { Can this be const? > + MISA_CFG(RVA, true), > + MISA_CFG(RVC, true), > + MISA_CFG(RVD, true), > + MISA_CFG(RVF, true), > + MISA_CFG(RVI, true), > + MISA_CFG(RVE, false), > + MISA_CFG(RVM, true), > + MISA_CFG(RVS, true), > + MISA_CFG(RVU, true), > + MISA_CFG(RVH, true), > + MISA_CFG(RVJ, false), > + MISA_CFG(RVV, false), > + MISA_CFG(RVG, false), > +}; > + > +static void riscv_cpu_add_misa_properties(Object *cpu_obj) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { > + RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; > + int bit = misa_cfg->misa_bit; > + > + misa_cfg->name = riscv_get_misa_ext_name(bit); > + misa_cfg->description = riscv_get_misa_ext_description(bit); > + > + object_property_add(cpu_obj, misa_cfg->name, "bool", > + cpu_get_misa_ext_cfg, > + cpu_set_misa_ext_cfg, > + NULL, (void *)misa_cfg); > + object_property_set_description(cpu_obj, misa_cfg->name, > + misa_cfg->description); > + object_property_set_bool(cpu_obj, misa_cfg->name, > + misa_cfg->enabled, NULL); > + } > +} > + > static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, > void *opaque, Error **errp) > { > -- > 2.41.0 > > Otherwise, Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
On 8/31/23 09:01, Andrew Jones wrote: > On Fri, Aug 25, 2023 at 10:08:49AM -0300, Daniel Henrique Barboza wrote: >> All code related to MISA TCG properties is also moved. >> >> At this point, all TCG properties handling is done in tcg-cpu.c, all KVM >> properties handling is done in kvm-cpu.c. >> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> --- >> target/riscv/cpu.c | 89 -------------------------------------- >> target/riscv/cpu.h | 1 - >> target/riscv/tcg/tcg-cpu.c | 84 +++++++++++++++++++++++++++++++++++ >> 3 files changed, 84 insertions(+), 90 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 89b09a7e89..3c9db46837 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -1201,49 +1201,6 @@ static void riscv_cpu_init(Object *obj) >> #endif /* CONFIG_USER_ONLY */ >> } >> >> -typedef struct RISCVCPUMisaExtConfig { >> - const char *name; >> - const char *description; >> - target_ulong misa_bit; >> - bool enabled; >> -} RISCVCPUMisaExtConfig; >> - >> -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, >> - void *opaque, Error **errp) >> -{ >> - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; >> - target_ulong misa_bit = misa_ext_cfg->misa_bit; >> - RISCVCPU *cpu = RISCV_CPU(obj); >> - CPURISCVState *env = &cpu->env; >> - bool value; >> - >> - if (!visit_type_bool(v, name, &value, errp)) { >> - return; >> - } >> - >> - if (value) { >> - env->misa_ext |= misa_bit; >> - env->misa_ext_mask |= misa_bit; >> - } else { >> - env->misa_ext &= ~misa_bit; >> - env->misa_ext_mask &= ~misa_bit; >> - } >> -} >> - >> -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, >> - void *opaque, Error **errp) >> -{ >> - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; >> - target_ulong misa_bit = misa_ext_cfg->misa_bit; >> - RISCVCPU *cpu = RISCV_CPU(obj); >> - CPURISCVState *env = &cpu->env; >> - bool value; >> - >> - value = env->misa_ext & misa_bit; >> - >> - visit_type_bool(v, name, &value, errp); >> -} >> - >> typedef struct misa_ext_info { >> const char *name; >> const char *description; >> @@ -1304,52 +1261,6 @@ const char *riscv_get_misa_ext_description(uint32_t bit) >> return val; >> } >> >> -#define MISA_CFG(_bit, _enabled) \ >> - {.misa_bit = _bit, .enabled = _enabled} >> - >> -static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { >> - MISA_CFG(RVA, true), >> - MISA_CFG(RVC, true), >> - MISA_CFG(RVD, true), >> - MISA_CFG(RVF, true), >> - MISA_CFG(RVI, true), >> - MISA_CFG(RVE, false), >> - MISA_CFG(RVM, true), >> - MISA_CFG(RVS, true), >> - MISA_CFG(RVU, true), >> - MISA_CFG(RVH, true), >> - MISA_CFG(RVJ, false), >> - MISA_CFG(RVV, false), >> - MISA_CFG(RVG, false), >> -}; >> - >> -void riscv_cpu_add_misa_properties(Object *cpu_obj) >> -{ >> - int i; >> - >> - for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { >> - RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; >> - int bit = misa_cfg->misa_bit; >> - >> - misa_cfg->name = riscv_get_misa_ext_name(bit); >> - misa_cfg->description = riscv_get_misa_ext_description(bit); >> - >> - /* Check if KVM already created the property */ >> - if (object_property_find(cpu_obj, misa_cfg->name)) { >> - continue; >> - } >> - >> - object_property_add(cpu_obj, misa_cfg->name, "bool", >> - cpu_get_misa_ext_cfg, >> - cpu_set_misa_ext_cfg, >> - NULL, (void *)misa_cfg); >> - object_property_set_description(cpu_obj, misa_cfg->name, >> - misa_cfg->description); >> - object_property_set_bool(cpu_obj, misa_cfg->name, >> - misa_cfg->enabled, NULL); >> - } >> -} >> - >> #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ >> {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ >> .enabled = _defval} >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index 74fbb33e09..4269523e24 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; >> extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; >> extern Property riscv_cpu_options[]; >> >> -void riscv_cpu_add_misa_properties(Object *cpu_obj); >> void riscv_add_satp_mode_properties(Object *obj); >> >> /* CSR function table */ >> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c >> index 68ce3cbcb9..8e3f55d3a6 100644 >> --- a/target/riscv/tcg/tcg-cpu.c >> +++ b/target/riscv/tcg/tcg-cpu.c >> @@ -574,6 +574,90 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) >> return true; >> } >> >> +typedef struct RISCVCPUMisaExtConfig { >> + const char *name; >> + const char *description; >> + target_ulong misa_bit; >> + bool enabled; >> +} RISCVCPUMisaExtConfig; >> + >> +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, >> + void *opaque, Error **errp) >> +{ >> + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; >> + target_ulong misa_bit = misa_ext_cfg->misa_bit; >> + RISCVCPU *cpu = RISCV_CPU(obj); >> + CPURISCVState *env = &cpu->env; >> + bool value; >> + >> + if (!visit_type_bool(v, name, &value, errp)) { >> + return; >> + } >> + >> + if (value) { >> + env->misa_ext |= misa_bit; >> + env->misa_ext_mask |= misa_bit; >> + } else { >> + env->misa_ext &= ~misa_bit; >> + env->misa_ext_mask &= ~misa_bit; >> + } >> +} >> + >> +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, >> + void *opaque, Error **errp) >> +{ >> + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; >> + target_ulong misa_bit = misa_ext_cfg->misa_bit; >> + RISCVCPU *cpu = RISCV_CPU(obj); >> + CPURISCVState *env = &cpu->env; >> + bool value; >> + >> + value = env->misa_ext & misa_bit; >> + >> + visit_type_bool(v, name, &value, errp); >> +} >> + >> +#define MISA_CFG(_bit, _enabled) \ >> + {.misa_bit = _bit, .enabled = _enabled} >> + >> +static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > > Can this be const? At this moment it can't because we're setting 'name' and 'description' for each element down there in riscv_cpu_add_misa_properties(). However, in a quick look it seems that we don't need these fields because we don't access 'name' or 'description' using the struct after the property is created. I'll take another look and, if that's indeed the case, I'll do a prep patch to make these changes before moving code in this patch. Thanks, Daniel > >> + MISA_CFG(RVA, true), >> + MISA_CFG(RVC, true), >> + MISA_CFG(RVD, true), >> + MISA_CFG(RVF, true), >> + MISA_CFG(RVI, true), >> + MISA_CFG(RVE, false), >> + MISA_CFG(RVM, true), >> + MISA_CFG(RVS, true), >> + MISA_CFG(RVU, true), >> + MISA_CFG(RVH, true), >> + MISA_CFG(RVJ, false), >> + MISA_CFG(RVV, false), >> + MISA_CFG(RVG, false), >> +}; >> + >> +static void riscv_cpu_add_misa_properties(Object *cpu_obj) >> +{ >> + int i; >> + >> + for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { >> + RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; >> + int bit = misa_cfg->misa_bit; >> + >> + misa_cfg->name = riscv_get_misa_ext_name(bit); >> + misa_cfg->description = riscv_get_misa_ext_description(bit); >> + >> + object_property_add(cpu_obj, misa_cfg->name, "bool", >> + cpu_get_misa_ext_cfg, >> + cpu_set_misa_ext_cfg, >> + NULL, (void *)misa_cfg); >> + object_property_set_description(cpu_obj, misa_cfg->name, >> + misa_cfg->description); >> + object_property_set_bool(cpu_obj, misa_cfg->name, >> + misa_cfg->enabled, NULL); >> + } >> +} >> + >> static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, >> void *opaque, Error **errp) >> { >> -- >> 2.41.0 >> >> > > Otherwise, > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 89b09a7e89..3c9db46837 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1201,49 +1201,6 @@ static void riscv_cpu_init(Object *obj) #endif /* CONFIG_USER_ONLY */ } -typedef struct RISCVCPUMisaExtConfig { - const char *name; - const char *description; - target_ulong misa_bit; - bool enabled; -} RISCVCPUMisaExtConfig; - -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; - target_ulong misa_bit = misa_ext_cfg->misa_bit; - RISCVCPU *cpu = RISCV_CPU(obj); - CPURISCVState *env = &cpu->env; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - if (value) { - env->misa_ext |= misa_bit; - env->misa_ext_mask |= misa_bit; - } else { - env->misa_ext &= ~misa_bit; - env->misa_ext_mask &= ~misa_bit; - } -} - -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; - target_ulong misa_bit = misa_ext_cfg->misa_bit; - RISCVCPU *cpu = RISCV_CPU(obj); - CPURISCVState *env = &cpu->env; - bool value; - - value = env->misa_ext & misa_bit; - - visit_type_bool(v, name, &value, errp); -} - typedef struct misa_ext_info { const char *name; const char *description; @@ -1304,52 +1261,6 @@ const char *riscv_get_misa_ext_description(uint32_t bit) return val; } -#define MISA_CFG(_bit, _enabled) \ - {.misa_bit = _bit, .enabled = _enabled} - -static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { - MISA_CFG(RVA, true), - MISA_CFG(RVC, true), - MISA_CFG(RVD, true), - MISA_CFG(RVF, true), - MISA_CFG(RVI, true), - MISA_CFG(RVE, false), - MISA_CFG(RVM, true), - MISA_CFG(RVS, true), - MISA_CFG(RVU, true), - MISA_CFG(RVH, true), - MISA_CFG(RVJ, false), - MISA_CFG(RVV, false), - MISA_CFG(RVG, false), -}; - -void riscv_cpu_add_misa_properties(Object *cpu_obj) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { - RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; - int bit = misa_cfg->misa_bit; - - misa_cfg->name = riscv_get_misa_ext_name(bit); - misa_cfg->description = riscv_get_misa_ext_description(bit); - - /* Check if KVM already created the property */ - if (object_property_find(cpu_obj, misa_cfg->name)) { - continue; - } - - object_property_add(cpu_obj, misa_cfg->name, "bool", - cpu_get_misa_ext_cfg, - cpu_set_misa_ext_cfg, - NULL, (void *)misa_cfg); - object_property_set_description(cpu_obj, misa_cfg->name, - misa_cfg->description); - object_property_set_bool(cpu_obj, misa_cfg->name, - misa_cfg->enabled, NULL); - } -} - #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ .enabled = _defval} diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 74fbb33e09..4269523e24 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern Property riscv_cpu_options[]; -void riscv_cpu_add_misa_properties(Object *cpu_obj); void riscv_add_satp_mode_properties(Object *obj); /* CSR function table */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 68ce3cbcb9..8e3f55d3a6 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -574,6 +574,90 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) return true; } +typedef struct RISCVCPUMisaExtConfig { + const char *name; + const char *description; + target_ulong misa_bit; + bool enabled; +} RISCVCPUMisaExtConfig; + +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; + target_ulong misa_bit = misa_ext_cfg->misa_bit; + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + env->misa_ext |= misa_bit; + env->misa_ext_mask |= misa_bit; + } else { + env->misa_ext &= ~misa_bit; + env->misa_ext_mask &= ~misa_bit; + } +} + +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; + target_ulong misa_bit = misa_ext_cfg->misa_bit; + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + bool value; + + value = env->misa_ext & misa_bit; + + visit_type_bool(v, name, &value, errp); +} + +#define MISA_CFG(_bit, _enabled) \ + {.misa_bit = _bit, .enabled = _enabled} + +static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { + MISA_CFG(RVA, true), + MISA_CFG(RVC, true), + MISA_CFG(RVD, true), + MISA_CFG(RVF, true), + MISA_CFG(RVI, true), + MISA_CFG(RVE, false), + MISA_CFG(RVM, true), + MISA_CFG(RVS, true), + MISA_CFG(RVU, true), + MISA_CFG(RVH, true), + MISA_CFG(RVJ, false), + MISA_CFG(RVV, false), + MISA_CFG(RVG, false), +}; + +static void riscv_cpu_add_misa_properties(Object *cpu_obj) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { + RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; + int bit = misa_cfg->misa_bit; + + misa_cfg->name = riscv_get_misa_ext_name(bit); + misa_cfg->description = riscv_get_misa_ext_description(bit); + + object_property_add(cpu_obj, misa_cfg->name, "bool", + cpu_get_misa_ext_cfg, + cpu_set_misa_ext_cfg, + NULL, (void *)misa_cfg); + object_property_set_description(cpu_obj, misa_cfg->name, + misa_cfg->description); + object_property_set_bool(cpu_obj, misa_cfg->name, + misa_cfg->enabled, NULL); + } +} + static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) {
All code related to MISA TCG properties is also moved. At this point, all TCG properties handling is done in tcg-cpu.c, all KVM properties handling is done in kvm-cpu.c. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 89 -------------------------------------- target/riscv/cpu.h | 1 - target/riscv/tcg/tcg-cpu.c | 84 +++++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+), 90 deletions(-)