Message ID | 20230825130853.511782-19-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | riscv: split TCG/KVM accelerators from cpu.c | expand |
On Fri, Aug 25, 2023 at 10:08:51AM -0300, Daniel Henrique Barboza wrote: > Priv spec validation is TCG specific. Move it to the TCG accel class. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.c | 39 -------------------------------------- > target/riscv/cpu.h | 2 -- > target/riscv/tcg/tcg-cpu.c | 39 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 39 insertions(+), 41 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ac5ad4727c..6817f94c2c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -172,22 +172,6 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en) > *ext_enabled = en; > } > > -int cpu_cfg_ext_get_min_version(uint32_t ext_offset) > -{ > - const RISCVIsaExtData *edata; > - > - for (edata = isa_edata_arr; edata && edata->name; edata++) { > - if (edata->ext_enable_offset != ext_offset) { > - continue; > - } > - > - return edata->min_version; > - } > - > - /* Default to oldest priv spec if no match found */ > - return PRIV_VERSION_1_10_0; > -} > - > const char * const riscv_int_regnames[] = { > "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", > "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", > @@ -926,29 +910,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > -{ > - CPURISCVState *env = &cpu->env; > - const RISCVIsaExtData *edata; > - > - /* Force disable extensions if priv spec version does not match */ > - for (edata = isa_edata_arr; edata && edata->name; edata++) { > - if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && > - (env->priv_ver < edata->min_version)) { > - isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); > -#ifndef CONFIG_USER_ONLY > - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx > - " because privilege spec version does not match", > - edata->name, env->mhartid); > -#else > - warn_report("disabling %s extension because " > - "privilege spec version does not match", > - edata->name); > -#endif > - } > - } > -} > - > #ifndef CONFIG_USER_ONLY > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index d9a17df46a..4254f04684 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -711,9 +711,7 @@ enum riscv_pmu_event_idx { > /* used by tcg/tcg-cpu.c*/ > void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); > bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); > -int cpu_cfg_ext_get_min_version(uint32_t ext_offset); > void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); > -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); > > typedef struct RISCVCPUMultiExtConfig { > const char *name; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 8e3f55d3a6..6c91978920 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -97,6 +97,22 @@ const struct TCGCPUOps riscv_tcg_ops = { > #endif /* !CONFIG_USER_ONLY */ > }; > > +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) > +{ > + const RISCVIsaExtData *edata; > + > + for (edata = isa_edata_arr; edata && edata->name; edata++) { > + if (edata->ext_enable_offset != ext_offset) { > + continue; > + } > + > + return edata->min_version; > + } > + > + /* Default to oldest priv spec if no match found */ > + return PRIV_VERSION_1_10_0; > +} > + > static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, > bool value) > { > @@ -220,6 +236,29 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > } > } > > +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > +{ > + CPURISCVState *env = &cpu->env; > + const RISCVIsaExtData *edata; > + > + /* Force disable extensions if priv spec version does not match */ > + for (edata = isa_edata_arr; edata && edata->name; edata++) { > + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && > + (env->priv_ver < edata->min_version)) { > + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); > +#ifndef CONFIG_USER_ONLY > + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx > + " because privilege spec version does not match", > + edata->name, env->mhartid); > +#else > + warn_report("disabling %s extension because " > + "privilege spec version does not match", > + edata->name); > +#endif > + } > + } > +} > + > /* > * Check consistency between chosen extensions while setting > * cpu->cfg accordingly. > -- > 2.41.0 > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac5ad4727c..6817f94c2c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -172,22 +172,6 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en) *ext_enabled = en; } -int cpu_cfg_ext_get_min_version(uint32_t ext_offset) -{ - const RISCVIsaExtData *edata; - - for (edata = isa_edata_arr; edata && edata->name; edata++) { - if (edata->ext_enable_offset != ext_offset) { - continue; - } - - return edata->min_version; - } - - /* Default to oldest priv spec if no match found */ - return PRIV_VERSION_1_10_0; -} - const char * const riscv_int_regnames[] = { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -926,29 +910,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) -{ - CPURISCVState *env = &cpu->env; - const RISCVIsaExtData *edata; - - /* Force disable extensions if priv spec version does not match */ - for (edata = isa_edata_arr; edata && edata->name; edata++) { - if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && - (env->priv_ver < edata->min_version)) { - isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx - " because privilege spec version does not match", - edata->name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - edata->name); -#endif - } - } -} - #ifndef CONFIG_USER_ONLY static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d9a17df46a..4254f04684 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -711,9 +711,7 @@ enum riscv_pmu_event_idx { /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); -int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8e3f55d3a6..6c91978920 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -97,6 +97,22 @@ const struct TCGCPUOps riscv_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +{ + const RISCVIsaExtData *edata; + + for (edata = isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset != ext_offset) { + continue; + } + + return edata->min_version; + } + + /* Default to oldest priv spec if no match found */ + return PRIV_VERSION_1_10_0; +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -220,6 +236,29 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, } } +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env = &cpu->env; + const RISCVIsaExtData *edata; + + /* Force disable extensions if priv spec version does not match */ + for (edata = isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && + (env->priv_ver < edata->min_version)) { + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + edata->name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + edata->name); +#endif + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly.
Priv spec validation is TCG specific. Move it to the TCG accel class. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 39 -------------------------------------- target/riscv/cpu.h | 2 -- target/riscv/tcg/tcg-cpu.c | 39 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 41 deletions(-)