Message ID | 20230811214031.171020-1-richard.henderson@linaro.org |
---|---|
Headers | show |
Series | target/arm: Implement cortex-a710 | expand |
On Fri, 11 Aug 2023 at 22:42, Richard Henderson <richard.henderson@linaro.org> wrote: > > This is one of the first generation Armv9 cores, and gives us something > concrete to test in that area. Notably, it supports MTE. > > Changes for v2: > * Check GMBS during realize. > * Fix access checks for neoverse implementation registers. > Mostly just traps EL1/EL2 if EL2/EL3 enabled. > * Add make_ccsidr64 helper. > * Reduce MTE with no tag memory to MTE=1. > * Suppress FEAT_TRBE. > * Implement HPDS2 as a no-op. > * Rewrite a710 implementation registers; do try to share code with > neoverse, because the traps are different. This of course solves > the renaming and renumbering issues too. > I've applied patches 1-7, 9 and 10 to target-arm.next. thanks -- PMM