@@ -33,4 +33,5 @@ C_O1_I2(r, rZ, ri)
C_O1_I2(r, rZ, rJ)
C_O1_I2(r, rZ, rZ)
C_O1_I2(w, w, w)
+C_O1_I3(w, w, w, w)
C_O1_I4(r, rZ, rJ, rZ, rZ)
@@ -1619,7 +1619,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
const int const_args[TCG_MAX_OP_ARGS])
{
TCGType type = vecl + TCG_TYPE_V64;
- TCGArg a0, a1, a2;
+ TCGArg a0, a1, a2, a3;
TCGReg base;
TCGReg temp = TCG_REG_TMP0;
int32_t offset;
@@ -1681,6 +1681,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
a0 = args[0];
a1 = args[1];
a2 = args[2];
+ a3 = args[3];
/* Currently only supports V128 */
tcg_debug_assert(type == TCG_TYPE_V128);
@@ -1790,6 +1791,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sarv_vec:
tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2));
break;
+ case INDEX_op_bitsel_vec:
+ /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
+ tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
+ break;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
@@ -1827,6 +1832,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+ case INDEX_op_bitsel_vec:
return 1;
default:
return 0;
@@ -2014,6 +2020,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_neg_vec:
return C_O1_I1(w, w);
+ case INDEX_op_bitsel_vec:
+ return C_O1_I3(w, w, w, w);
+
default:
g_assert_not_reached();
}
@@ -191,7 +191,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_rotv_vec 0
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
Signed-off-by: Jiajie Chen <c@jia.je> --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 11 ++++++++++- tcg/loongarch64/tcg-target.h | 2 +- 3 files changed, 12 insertions(+), 2 deletions(-)