diff mbox series

[v2,4/5] target/loongarch: Support LoongArch32 TLB entry

Message ID 20230807031850.1961130-4-c@jia.je
State New
Headers show
Series [v2,1/5] target/loongarch: Add loongarch32 mode for loongarch64-softmmu | expand

Commit Message

Jiajie Chen Aug. 7, 2023, 3:18 a.m. UTC 
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 target/loongarch/cpu-csr.h    |  9 +++++----
 target/loongarch/tlb_helper.c | 17 ++++++++++++-----
 2 files changed, 17 insertions(+), 9 deletions(-)

Comments

Jiajie Chen Aug. 7, 2023, 5:17 a.m. UTC | #1 
On 2023/8/7 11:18, Jiajie Chen wrote:
> The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
> zero in LoongArch32.
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   target/loongarch/cpu-csr.h    |  9 +++++----
>   target/loongarch/tlb_helper.c | 17 ++++++++++++-----
>   2 files changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
> index f8f24032cb..faf76a589b 100644
> --- a/target/loongarch/cpu-csr.h
> +++ b/target/loongarch/cpu-csr.h
> @@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
>   FIELD(TLBENTRY, PLV, 2, 2)
>   FIELD(TLBENTRY, MAT, 4, 2)
>   FIELD(TLBENTRY, G, 6, 1)
> -FIELD(TLBENTRY, PPN, 12, 36)
> -FIELD(TLBENTRY, NR, 61, 1)
> -FIELD(TLBENTRY, NX, 62, 1)
> -FIELD(TLBENTRY, RPLV, 63, 1)
> +FIELD(TLBENTRY_32, PPN, 12, 24)

Sorry, the starting bit of TLBENTRY_32_PPN should be 8 instead of 12. 
Will be corrected in v3.


> +FIELD(TLBENTRY_64, PPN, 12, 36)
> +FIELD(TLBENTRY_64, NR, 61, 1)
> +FIELD(TLBENTRY_64, NX, 62, 1)
> +FIELD(TLBENTRY_64, RPLV, 63, 1)
>   
>   #define LOONGARCH_CSR_ASID           0x18 /* Address space identifier */
>   FIELD(CSR_ASID, ASID, 0, 10)
> diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
> index 6e00190547..690c6ef25f 100644
> --- a/target/loongarch/tlb_helper.c
> +++ b/target/loongarch/tlb_helper.c
> @@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>       tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
>       tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
>       tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
> -    tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
> -    tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
> -    tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
> -    tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
> +    if (env->mode == LA64) {
> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
> +        tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
> +        tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
> +        tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
> +    } else {
> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
> +        tlb_nx = 0;
> +        tlb_nr = 0;
> +        tlb_rplv = 0;
> +    }
>   
>       /* Check access rights */
>       if (!tlb_v) {
> @@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>        * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
>        * need adjust.
>        */
> -    *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
> +    *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
>                   (address & MAKE_64BIT_MASK(0, tlb_ps));
>       *prot = PAGE_READ;
>       if (tlb_d) {
Song Gao Aug. 7, 2023, 6:55 a.m. UTC | #2 
Hi, Jiajie

在 2023/8/7 下午1:17, Jiajie Chen 写道:
> 
> On 2023/8/7 11:18, Jiajie Chen wrote:
>> The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
>> zero in LoongArch32.
>>
>> Signed-off-by: Jiajie Chen <c@jia.je>
>> ---
>>   target/loongarch/cpu-csr.h    |  9 +++++----
>>   target/loongarch/tlb_helper.c | 17 ++++++++++++-----
>>   2 files changed, 17 insertions(+), 9 deletions(-)
>>
Please
Cc: Richard Henderson <richard.henderson@linaro.org>

And
Cc: Jun Yi <yijun@loongson.cn>
CC: shenjinyang@loongson.cn>
Their are also interested with Loongarch32 softmmu.

It would be better use the parameter '--cover-letter' create a patch0.
Add some Change logs and introduction about this series in patch0.

Thanks.
Song Gao
>> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
>> index f8f24032cb..faf76a589b 100644
>> --- a/target/loongarch/cpu-csr.h
>> +++ b/target/loongarch/cpu-csr.h
>> @@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
>>   FIELD(TLBENTRY, PLV, 2, 2)
>>   FIELD(TLBENTRY, MAT, 4, 2)
>>   FIELD(TLBENTRY, G, 6, 1)
>> -FIELD(TLBENTRY, PPN, 12, 36)
>> -FIELD(TLBENTRY, NR, 61, 1)
>> -FIELD(TLBENTRY, NX, 62, 1)
>> -FIELD(TLBENTRY, RPLV, 63, 1)
>> +FIELD(TLBENTRY_32, PPN, 12, 24)
> 
> Sorry, the starting bit of TLBENTRY_32_PPN should be 8 instead of 12. 
> Will be corrected in v3.
> 
> 
>> +FIELD(TLBENTRY_64, PPN, 12, 36)
>> +FIELD(TLBENTRY_64, NR, 61, 1)
>> +FIELD(TLBENTRY_64, NX, 62, 1)
>> +FIELD(TLBENTRY_64, RPLV, 63, 1)
>>   #define LOONGARCH_CSR_ASID           0x18 /* Address space 
>> identifier */
>>   FIELD(CSR_ASID, ASID, 0, 10)
>> diff --git a/target/loongarch/tlb_helper.c 
>> b/target/loongarch/tlb_helper.c
>> index 6e00190547..690c6ef25f 100644
>> --- a/target/loongarch/tlb_helper.c
>> +++ b/target/loongarch/tlb_helper.c
>> @@ -48,10 +48,17 @@ static int 
>> loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>>       tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
>>       tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
>>       tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
>> -    tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
>> -    tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
>> -    tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
>> -    tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
>> +    if (env->mode == LA64) {
>> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
>> +        tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
>> +        tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
>> +        tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
>> +    } else {
>> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
>> +        tlb_nx = 0;
>> +        tlb_nr = 0;
>> +        tlb_rplv = 0;
>> +    }
>>       /* Check access rights */
>>       if (!tlb_v) {
>> @@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState 
>> *env, hwaddr *physical,
>>        * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
>>        * need adjust.
>>        */
>> -    *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
>> +    *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
>>                   (address & MAKE_64BIT_MASK(0, tlb_ps));
>>       *prot = PAGE_READ;
>>       if (tlb_d) {
Jiajie Chen Aug. 7, 2023, 8:23 a.m. UTC | #3 
On 2023/8/7 14:55, gaosong wrote:
> Hi, Jiajie
>
> 在 2023/8/7 下午1:17, Jiajie Chen 写道:
>>
>> On 2023/8/7 11:18, Jiajie Chen wrote:
>>> The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
>>> zero in LoongArch32.
>>>
>>> Signed-off-by: Jiajie Chen <c@jia.je>
>>> ---
>>>   target/loongarch/cpu-csr.h    |  9 +++++----
>>>   target/loongarch/tlb_helper.c | 17 ++++++++++++-----
>>>   2 files changed, 17 insertions(+), 9 deletions(-)
>>>
> Please
> Cc: Richard Henderson <richard.henderson@linaro.org>
>
> And
> Cc: Jun Yi <yijun@loongson.cn>
> CC: shenjinyang@loongson.cn>
> Their are also interested with Loongarch32 softmmu.
>
> It would be better use the parameter '--cover-letter' create a patch0.
> Add some Change logs and introduction about this series in patch0.

Thanks, I will add this in my next version of patch series.

> Thanks.
> Song Gao
>>> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
>>> index f8f24032cb..faf76a589b 100644
>>> --- a/target/loongarch/cpu-csr.h
>>> +++ b/target/loongarch/cpu-csr.h
>>> @@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
>>>   FIELD(TLBENTRY, PLV, 2, 2)
>>>   FIELD(TLBENTRY, MAT, 4, 2)
>>>   FIELD(TLBENTRY, G, 6, 1)
>>> -FIELD(TLBENTRY, PPN, 12, 36)
>>> -FIELD(TLBENTRY, NR, 61, 1)
>>> -FIELD(TLBENTRY, NX, 62, 1)
>>> -FIELD(TLBENTRY, RPLV, 63, 1)
>>> +FIELD(TLBENTRY_32, PPN, 12, 24)
>>
>> Sorry, the starting bit of TLBENTRY_32_PPN should be 8 instead of 12. 
>> Will be corrected in v3.
>>
>>
>>> +FIELD(TLBENTRY_64, PPN, 12, 36)
>>> +FIELD(TLBENTRY_64, NR, 61, 1)
>>> +FIELD(TLBENTRY_64, NX, 62, 1)
>>> +FIELD(TLBENTRY_64, RPLV, 63, 1)
>>>   #define LOONGARCH_CSR_ASID           0x18 /* Address space 
>>> identifier */
>>>   FIELD(CSR_ASID, ASID, 0, 10)
>>> diff --git a/target/loongarch/tlb_helper.c 
>>> b/target/loongarch/tlb_helper.c
>>> index 6e00190547..690c6ef25f 100644
>>> --- a/target/loongarch/tlb_helper.c
>>> +++ b/target/loongarch/tlb_helper.c
>>> @@ -48,10 +48,17 @@ static int 
>>> loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>>>       tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
>>>       tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
>>>       tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
>>> -    tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
>>> -    tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
>>> -    tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
>>> -    tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
>>> +    if (env->mode == LA64) {
>>> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
>>> +        tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
>>> +        tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
>>> +        tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
>>> +    } else {
>>> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
>>> +        tlb_nx = 0;
>>> +        tlb_nr = 0;
>>> +        tlb_rplv = 0;
>>> +    }
>>>       /* Check access rights */
>>>       if (!tlb_v) {
>>> @@ -79,7 +86,7 @@ static int 
>>> loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>>>        * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
>>>        * need adjust.
>>>        */
>>> -    *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
>>> +    *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
>>>                   (address & MAKE_64BIT_MASK(0, tlb_ps));
>>>       *prot = PAGE_READ;
>>>       if (tlb_d) {
>
diff mbox series

Patch

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index f8f24032cb..faf76a589b 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -66,10 +66,11 @@  FIELD(TLBENTRY, D, 1, 1)
 FIELD(TLBENTRY, PLV, 2, 2)
 FIELD(TLBENTRY, MAT, 4, 2)
 FIELD(TLBENTRY, G, 6, 1)
-FIELD(TLBENTRY, PPN, 12, 36)
-FIELD(TLBENTRY, NR, 61, 1)
-FIELD(TLBENTRY, NX, 62, 1)
-FIELD(TLBENTRY, RPLV, 63, 1)
+FIELD(TLBENTRY_32, PPN, 12, 24)
+FIELD(TLBENTRY_64, PPN, 12, 36)
+FIELD(TLBENTRY_64, NR, 61, 1)
+FIELD(TLBENTRY_64, NX, 62, 1)
+FIELD(TLBENTRY_64, RPLV, 63, 1)
 
 #define LOONGARCH_CSR_ASID           0x18 /* Address space identifier */
 FIELD(CSR_ASID, ASID, 0, 10)
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 6e00190547..690c6ef25f 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -48,10 +48,17 @@  static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
     tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
     tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
     tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
-    tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
-    tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
-    tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
-    tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
+    if (env->mode == LA64) {
+        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
+        tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
+        tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
+        tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
+    } else {
+        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
+        tlb_nx = 0;
+        tlb_nr = 0;
+        tlb_rplv = 0;
+    }
 
     /* Check access rights */
     if (!tlb_v) {
@@ -79,7 +86,7 @@  static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
      * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
      * need adjust.
      */
-    *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
+    *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
                 (address & MAKE_64BIT_MASK(0, tlb_ps));
     *prot = PAGE_READ;
     if (tlb_d) {