Message ID | 20230714154648.327466-2-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show |
Series | target/arm/ptw: Cleanups and a few bugfixes | expand |
On 7/14/23 16:46, Peter Maydell wrote: > For an Unsupported Atomic Update fault where the stage 1 translation > table descriptor update can't be done because it's to an unsupported > memory type, this is a stage 1 abort (per the Arm ARM R_VSXXT). This > means we should not set fi->s1ptw, because this will cause the code > in the get_phys_addr_lpae() error-exit path to mark it as stage 2. > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > target/arm/ptw.c | 1 - > 1 file changed, 1 deletion(-) Confusingly named, but correctly documented. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8f94100c61f..bafeb876ad7 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -701,7 +701,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, if (unlikely(!host)) { fi->type = ARMFault_UnsuppAtomicUpdate; - fi->s1ptw = true; return 0; }
For an Unsupported Atomic Update fault where the stage 1 translation table descriptor update can't be done because it's to an unsupported memory type, this is a stage 1 abort (per the Arm ARM R_VSXXT). This means we should not set fi->s1ptw, because this will cause the code in the get_phys_addr_lpae() error-exit path to mark it as stage 2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/ptw.c | 1 - 1 file changed, 1 deletion(-)