Message ID | 2d1159457cd395dafbc5de3c4b4e3c5137af5e1a.1688421085.git.balaton@eik.bme.hu |
---|---|
State | New |
Headers | show |
Series | PPC440 devices misc clean up | expand |
On 4/7/23 00:02, BALATON Zoltan wrote: > Add separate memory regions for the mem and io spaces of the PCIe bus > to avoid different buses using the same system io region. "Reduce the I/O space to 64K." > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > --- > hw/ppc/ppc440_uc.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c > index 38ee27f437..0c5d999878 100644 > --- a/hw/ppc/ppc440_uc.c > +++ b/hw/ppc/ppc440_uc.c > @@ -776,6 +776,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST) > struct PPC460EXPCIEState { > PCIExpressHost host; > > + MemoryRegion busmem; > MemoryRegion iomem; > qemu_irq irq[4]; > int32_t dcrn_base; > @@ -1056,15 +1057,17 @@ static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) > error_setg(errp, "invalid PCIe DCRN base"); > return; > } > + snprintf(buf, sizeof(buf), "pcie%d-mem", id); > + memory_region_init(&s->busmem, OBJECT(s), buf, UINT64_MAX); > snprintf(buf, sizeof(buf), "pcie%d-io", id); > - memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); > + memory_region_init(&s->iomem, OBJECT(s), buf, 0x10000); 64 * KiB > for (i = 0; i < 4; i++) { > sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); > } > snprintf(buf, sizeof(buf), "pcie.%d", id); > pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, > - pci_swizzle_map_irq_fn, s, &s->iomem, > - get_system_io(), 0, 4, TYPE_PCIE_BUS); > + pci_swizzle_map_irq_fn, s, &s->busmem, > + &s->iomem, 0, 4, TYPE_PCIE_BUS); > ppc460ex_pcie_register_dcrs(s); > } > With the changes addressed: Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On Tue, 4 Jul 2023, Philippe Mathieu-Daudé wrote: > On 4/7/23 00:02, BALATON Zoltan wrote: >> Add separate memory regions for the mem and io spaces of the PCIe bus >> to avoid different buses using the same system io region. > > "Reduce the I/O space to 64K." Unlike the other similar patch this does not reduce the IO space size because get_system_io() was that size already. I've changed the size below to use KiB. Regards, BALATON Zoltan >> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> >> --- >> hw/ppc/ppc440_uc.c | 9 ++++++--- >> 1 file changed, 6 insertions(+), 3 deletions(-) >> >> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c >> index 38ee27f437..0c5d999878 100644 >> --- a/hw/ppc/ppc440_uc.c >> +++ b/hw/ppc/ppc440_uc.c >> @@ -776,6 +776,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, >> PPC460EX_PCIE_HOST) >> struct PPC460EXPCIEState { >> PCIExpressHost host; >> + MemoryRegion busmem; >> MemoryRegion iomem; >> qemu_irq irq[4]; >> int32_t dcrn_base; >> @@ -1056,15 +1057,17 @@ static void ppc460ex_pcie_realize(DeviceState *dev, >> Error **errp) >> error_setg(errp, "invalid PCIe DCRN base"); >> return; >> } >> + snprintf(buf, sizeof(buf), "pcie%d-mem", id); >> + memory_region_init(&s->busmem, OBJECT(s), buf, UINT64_MAX); >> snprintf(buf, sizeof(buf), "pcie%d-io", id); >> - memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); >> + memory_region_init(&s->iomem, OBJECT(s), buf, 0x10000); > > 64 * KiB > >> for (i = 0; i < 4; i++) { >> sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); >> } >> snprintf(buf, sizeof(buf), "pcie.%d", id); >> pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, >> - pci_swizzle_map_irq_fn, s, &s->iomem, >> - get_system_io(), 0, 4, TYPE_PCIE_BUS); >> + pci_swizzle_map_irq_fn, s, &s->busmem, >> + &s->iomem, 0, 4, TYPE_PCIE_BUS); >> ppc460ex_pcie_register_dcrs(s); >> } >> > > With the changes addressed: > > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > > >
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 38ee27f437..0c5d999878 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -776,6 +776,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST) struct PPC460EXPCIEState { PCIExpressHost host; + MemoryRegion busmem; MemoryRegion iomem; qemu_irq irq[4]; int32_t dcrn_base; @@ -1056,15 +1057,17 @@ static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) error_setg(errp, "invalid PCIe DCRN base"); return; } + snprintf(buf, sizeof(buf), "pcie%d-mem", id); + memory_region_init(&s->busmem, OBJECT(s), buf, UINT64_MAX); snprintf(buf, sizeof(buf), "pcie%d-io", id); - memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); + memory_region_init(&s->iomem, OBJECT(s), buf, 0x10000); for (i = 0; i < 4; i++) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); } snprintf(buf, sizeof(buf), "pcie.%d", id); pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, - pci_swizzle_map_irq_fn, s, &s->iomem, - get_system_io(), 0, 4, TYPE_PCIE_BUS); + pci_swizzle_map_irq_fn, s, &s->busmem, + &s->iomem, 0, 4, TYPE_PCIE_BUS); ppc460ex_pcie_register_dcrs(s); }
Add separate memory regions for the mem and io spaces of the PCIe bus to avoid different buses using the same system io region. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> --- hw/ppc/ppc440_uc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)