| Message ID | 20230704054204.168547-4-joel@jms.id.au |
|---|---|
| State | New |
| Headers | show |
| Series | ppc/pnv: Extend "quad" model for p10 | expand |
On 7/4/23 07:42, Joel Stanley wrote: > Add a PnvQuad class for the P10 powernv machine. No xscoms are > implemented yet, but this allows them to be added. > > The size is reduced to avoid the quad region from overlapping with the > core region. > > address-space: xscom-0 > 0000000000000000-00000003ffffffff (prio 0, i/o): xscom-0 > 0000000100000000-00000001000fffff (prio 0, i/o): xscom-quad.0 > 0000000100108000-0000000100907fff (prio 0, i/o): xscom-core.3 > 0000000100110000-000000010090ffff (prio 0, i/o): xscom-core.2 > 0000000100120000-000000010091ffff (prio 0, i/o): xscom-core.1 > 0000000100140000-000000010093ffff (prio 0, i/o): xscom-core.0 > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > v2: Fix unimp read message > Wrap lines at 80 col > Set size > --- > include/hw/ppc/pnv_xscom.h | 2 +- > hw/ppc/pnv.c | 2 +- > hw/ppc/pnv_core.c | 54 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 56 insertions(+), 2 deletions(-) > > diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h > index cbe848d27ba0..f7da9a1dc617 100644 > --- a/include/hw/ppc/pnv_xscom.h > +++ b/include/hw/ppc/pnv_xscom.h > @@ -129,7 +129,7 @@ struct PnvXScomInterfaceClass { > > #define PNV10_XSCOM_EQ_BASE(core) \ > ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core))) > -#define PNV10_XSCOM_EQ_SIZE 0x100000 > +#define PNV10_XSCOM_EQ_SIZE 0x20000 > > #define PNV10_XSCOM_EC_BASE(core) \ > ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index c77fdb6747a4..5f25fe985ab2 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) > PnvQuad *eq = &chip10->quads[i]; > > pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], > - PNV_QUAD_TYPE_NAME("power9")); > + PNV_QUAD_TYPE_NAME("power10")); > > pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), > &eq->xscom_regs); > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 73d25409c937..e4df435b15e9 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = { > .endianness = DEVICE_BIG_ENDIAN, > }; > > +/* > + * POWER10 Quads > + */ > + > +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > + unsigned int width) > +{ > + uint32_t offset = addr >> 3; > + uint64_t val = -1; > + > + switch (offset) { > + default: > + qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__, > + offset); > + } > + > + return val; > +} > + > +static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, > + uint64_t val, unsigned int width) > +{ > + uint32_t offset = addr >> 3; > + > + switch (offset) { > + default: > + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > + offset); > + } > +} > + > +static const MemoryRegionOps pnv_quad_power10_xscom_ops = { > + .read = pnv_quad_power10_xscom_read, > + .write = pnv_quad_power10_xscom_write, > + .valid.min_access_size = 8, > + .valid.max_access_size = 8, > + .impl.min_access_size = 8, > + .impl.max_access_size = 8, > + .endianness = DEVICE_BIG_ENDIAN, > +}; > + > static void pnv_quad_realize(DeviceState *dev, Error **errp) > { > PnvQuad *eq = PNV_QUAD(dev); > @@ -430,6 +471,14 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) > pqc->xscom_size = PNV9_XSCOM_EQ_SIZE; > } > > +static void pnv_quad_power10_class_init(ObjectClass *oc, void *data) > +{ > + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); > + > + pqc->xscom_ops = &pnv_quad_power10_xscom_ops; > + pqc->xscom_size = PNV10_XSCOM_EQ_SIZE; > +} > + > static void pnv_quad_class_init(ObjectClass *oc, void *data) > { > DeviceClass *dc = DEVICE_CLASS(oc); > @@ -453,6 +502,11 @@ static const TypeInfo pnv_quad_infos[] = { > .name = PNV_QUAD_TYPE_NAME("power9"), > .class_init = pnv_quad_power9_class_init, > }, > + { > + .parent = TYPE_PNV_QUAD, > + .name = PNV_QUAD_TYPE_NAME("power10"), > + .class_init = pnv_quad_power10_class_init, > + }, > }; > > DEFINE_TYPES(pnv_quad_infos);
On 04/07/2023 07:42, Joel Stanley wrote: > Add a PnvQuad class for the P10 powernv machine. No xscoms are > implemented yet, but this allows them to be added. > > The size is reduced to avoid the quad region from overlapping with the > core region. > > address-space: xscom-0 > 0000000000000000-00000003ffffffff (prio 0, i/o): xscom-0 > 0000000100000000-00000001000fffff (prio 0, i/o): xscom-quad.0 > 0000000100108000-0000000100907fff (prio 0, i/o): xscom-core.3 > 0000000100110000-000000010090ffff (prio 0, i/o): xscom-core.2 > 0000000100120000-000000010091ffff (prio 0, i/o): xscom-core.1 > 0000000100140000-000000010093ffff (prio 0, i/o): xscom-core.0 > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Fred > v2: Fix unimp read message > Wrap lines at 80 col > Set size > --- > include/hw/ppc/pnv_xscom.h | 2 +- > hw/ppc/pnv.c | 2 +- > hw/ppc/pnv_core.c | 54 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 56 insertions(+), 2 deletions(-) > > diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h > index cbe848d27ba0..f7da9a1dc617 100644 > --- a/include/hw/ppc/pnv_xscom.h > +++ b/include/hw/ppc/pnv_xscom.h > @@ -129,7 +129,7 @@ struct PnvXScomInterfaceClass { > > #define PNV10_XSCOM_EQ_BASE(core) \ > ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core))) > -#define PNV10_XSCOM_EQ_SIZE 0x100000 > +#define PNV10_XSCOM_EQ_SIZE 0x20000 > > #define PNV10_XSCOM_EC_BASE(core) \ > ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index c77fdb6747a4..5f25fe985ab2 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) > PnvQuad *eq = &chip10->quads[i]; > > pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], > - PNV_QUAD_TYPE_NAME("power9")); > + PNV_QUAD_TYPE_NAME("power10")); > > pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), > &eq->xscom_regs); > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 73d25409c937..e4df435b15e9 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = { > .endianness = DEVICE_BIG_ENDIAN, > }; > > +/* > + * POWER10 Quads > + */ > + > +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > + unsigned int width) > +{ > + uint32_t offset = addr >> 3; > + uint64_t val = -1; > + > + switch (offset) { > + default: > + qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__, > + offset); > + } > + > + return val; > +} > + > +static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, > + uint64_t val, unsigned int width) > +{ > + uint32_t offset = addr >> 3; > + > + switch (offset) { > + default: > + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > + offset); > + } > +} > + > +static const MemoryRegionOps pnv_quad_power10_xscom_ops = { > + .read = pnv_quad_power10_xscom_read, > + .write = pnv_quad_power10_xscom_write, > + .valid.min_access_size = 8, > + .valid.max_access_size = 8, > + .impl.min_access_size = 8, > + .impl.max_access_size = 8, > + .endianness = DEVICE_BIG_ENDIAN, > +}; > + > static void pnv_quad_realize(DeviceState *dev, Error **errp) > { > PnvQuad *eq = PNV_QUAD(dev); > @@ -430,6 +471,14 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) > pqc->xscom_size = PNV9_XSCOM_EQ_SIZE; > } > > +static void pnv_quad_power10_class_init(ObjectClass *oc, void *data) > +{ > + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); > + > + pqc->xscom_ops = &pnv_quad_power10_xscom_ops; > + pqc->xscom_size = PNV10_XSCOM_EQ_SIZE; > +} > + > static void pnv_quad_class_init(ObjectClass *oc, void *data) > { > DeviceClass *dc = DEVICE_CLASS(oc); > @@ -453,6 +502,11 @@ static const TypeInfo pnv_quad_infos[] = { > .name = PNV_QUAD_TYPE_NAME("power9"), > .class_init = pnv_quad_power9_class_init, > }, > + { > + .parent = TYPE_PNV_QUAD, > + .name = PNV_QUAD_TYPE_NAME("power10"), > + .class_init = pnv_quad_power10_class_init, > + }, > }; > > DEFINE_TYPES(pnv_quad_infos);
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index cbe848d27ba0..f7da9a1dc617 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -129,7 +129,7 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_EQ_BASE(core) \ ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core))) -#define PNV10_XSCOM_EQ_SIZE 0x100000 +#define PNV10_XSCOM_EQ_SIZE 0x20000 #define PNV10_XSCOM_EC_BASE(core) \ ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c77fdb6747a4..5f25fe985ab2 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) PnvQuad *eq = &chip10->quads[i]; pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], - PNV_QUAD_TYPE_NAME("power9")); + PNV_QUAD_TYPE_NAME("power10")); pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), &eq->xscom_regs); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 73d25409c937..e4df435b15e9 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = { .endianness = DEVICE_BIG_ENDIAN, }; +/* + * POWER10 Quads + */ + +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, + unsigned int width) +{ + uint32_t offset = addr >> 3; + uint64_t val = -1; + + switch (offset) { + default: + qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__, + offset); + } + + return val; +} + +static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int width) +{ + uint32_t offset = addr >> 3; + + switch (offset) { + default: + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + offset); + } +} + +static const MemoryRegionOps pnv_quad_power10_xscom_ops = { + .read = pnv_quad_power10_xscom_read, + .write = pnv_quad_power10_xscom_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + static void pnv_quad_realize(DeviceState *dev, Error **errp) { PnvQuad *eq = PNV_QUAD(dev); @@ -430,6 +471,14 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) pqc->xscom_size = PNV9_XSCOM_EQ_SIZE; } +static void pnv_quad_power10_class_init(ObjectClass *oc, void *data) +{ + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); + + pqc->xscom_ops = &pnv_quad_power10_xscom_ops; + pqc->xscom_size = PNV10_XSCOM_EQ_SIZE; +} + static void pnv_quad_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -453,6 +502,11 @@ static const TypeInfo pnv_quad_infos[] = { .name = PNV_QUAD_TYPE_NAME("power9"), .class_init = pnv_quad_power9_class_init, }, + { + .parent = TYPE_PNV_QUAD, + .name = PNV_QUAD_TYPE_NAME("power10"), + .class_init = pnv_quad_power10_class_init, + }, }; DEFINE_TYPES(pnv_quad_infos);
Add a PnvQuad class for the P10 powernv machine. No xscoms are implemented yet, but this allows them to be added. The size is reduced to avoid the quad region from overlapping with the core region. address-space: xscom-0 0000000000000000-00000003ffffffff (prio 0, i/o): xscom-0 0000000100000000-00000001000fffff (prio 0, i/o): xscom-quad.0 0000000100108000-0000000100907fff (prio 0, i/o): xscom-core.3 0000000100110000-000000010090ffff (prio 0, i/o): xscom-core.2 0000000100120000-000000010091ffff (prio 0, i/o): xscom-core.1 0000000100140000-000000010093ffff (prio 0, i/o): xscom-core.0 Signed-off-by: Joel Stanley <joel@jms.id.au> --- v2: Fix unimp read message Wrap lines at 80 col Set size --- include/hw/ppc/pnv_xscom.h | 2 +- hw/ppc/pnv.c | 2 +- hw/ppc/pnv_core.c | 54 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 2 deletions(-)