Message ID | 20230622094346.29853-1-ivan.klokov@syntacore.com |
---|---|
State | New |
Headers | show |
Series | [v4,1/1] target/riscv: Add RVV registers to log | expand |
On 6/22/23 06:43, Ivan Klokov wrote: > Print RvV extesion register to log if VPU option is enabled. Typo: extesion -> extension > > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> > --- > v4: > - General part of patch has been merged, rebase riscv part and resend. > --- > target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 55 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index fb8458bf74..b23f3fde0d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -183,6 +183,14 @@ const char * const riscv_fpr_regnames[] = { > "f30/ft10", "f31/ft11" > }; > > +const char * const riscv_rvv_regnames[] = { > + "v0", "v1", "v2", "v3", "v4", "v5", "v6", > + "v7", "v8", "v9", "v10", "v11", "v12", "v13", > + "v14", "v15", "v16", "v17", "v18", "v19", "v20", > + "v21", "v22", "v23", "v24", "v25", "v26", "v27", > + "v28", "v29", "v30", "v31" > +}; > + > static const char * const riscv_excp_names[] = { > "misaligned_fetch", > "fault_fetch", > @@ -611,7 +619,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > { > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > - int i; > + int i, j; > + uint8_t *p; > > #if !defined(CONFIG_USER_ONLY) > if (riscv_has_ext(env, RVH)) { > @@ -695,6 +704,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > } > } > } > + if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { > + static const int dump_rvv_csrs[] = { > + CSR_VSTART, > + CSR_VXSAT, > + CSR_VXRM, > + CSR_VCSR, > + CSR_VL, > + CSR_VTYPE, > + CSR_VLENB, > + }; > + for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { > + int csrno = dump_rvv_csrs[i]; > + target_ulong val = 0; > + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); > + > + /* > + * Rely on the smode, hmode, etc, predicates within csr.c > + * to do the filtering of the registers that are present. > + */ > + if (res == RISCV_EXCP_NONE) { > + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", > + csr_ops[csrno].name, val); > + } > + } > + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; We have a "RISCVCPU *cpu" pointer available at the start of the function. Use that to access the cfg obj and avoid an unneeded env_archcpu() call: > + uint16_t vlenb = cpu->cfg.vlen >> 3; > + > +/* > + * From vector_helper.c > + * Note that vector data is stored in host-endian 64-bit chunks, > + * so addressing bytes needs a host-endian fixup. > + */ > +#if HOST_BIG_ENDIAN > +#define BYTE(x) ((x) ^ 7) > +#else > +#define BYTE(x) (x) > +#endif Usually we don't declare new macros in the middle of functions. I suggest moving this #define block to outside of riscv_cpu_dump_state() to keep the code more line with the current code style we use. Thanks, Daniel > + for (i = 0; i < 32; i++) { > + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); > + p = (uint8_t *)env->vreg; > + for (j = vlenb - 1 ; j >= 0; j--) { > + qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); > + } > + qemu_fprintf(f, "\n"); > + } > + } > } > > static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fb8458bf74..b23f3fde0d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -183,6 +183,14 @@ const char * const riscv_fpr_regnames[] = { "f30/ft10", "f31/ft11" }; +const char * const riscv_rvv_regnames[] = { + "v0", "v1", "v2", "v3", "v4", "v5", "v6", + "v7", "v8", "v9", "v10", "v11", "v12", "v13", + "v14", "v15", "v16", "v17", "v18", "v19", "v20", + "v21", "v22", "v23", "v24", "v25", "v26", "v27", + "v28", "v29", "v30", "v31" +}; + static const char * const riscv_excp_names[] = { "misaligned_fetch", "fault_fetch", @@ -611,7 +619,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - int i; + int i, j; + uint8_t *p; #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { @@ -695,6 +704,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } } + if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { + static const int dump_rvv_csrs[] = { + CSR_VSTART, + CSR_VXSAT, + CSR_VXRM, + CSR_VCSR, + CSR_VL, + CSR_VTYPE, + CSR_VLENB, + }; + for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { + int csrno = dump_rvv_csrs[i]; + target_ulong val = 0; + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); + + /* + * Rely on the smode, hmode, etc, predicates within csr.c + * to do the filtering of the registers that are present. + */ + if (res == RISCV_EXCP_NONE) { + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + csr_ops[csrno].name, val); + } + } + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + +/* + * From vector_helper.c + * Note that vector data is stored in host-endian 64-bit chunks, + * so addressing bytes needs a host-endian fixup. + */ +#if HOST_BIG_ENDIAN +#define BYTE(x) ((x) ^ 7) +#else +#define BYTE(x) (x) +#endif + for (i = 0; i < 32; i++) { + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); + p = (uint8_t *)env->vreg; + for (j = vlenb - 1 ; j >= 0; j--) { + qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); + } + qemu_fprintf(f, "\n"); + } + } } static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
Print RvV extesion register to log if VPU option is enabled. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> --- v4: - General part of patch has been merged, rebase riscv part and resend. --- target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-)