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[4/7] target/i386: TCG supports 32-bit SYSCALL

Message ID 20230618215114.107337-5-pbonzini@redhat.com
State New
Headers show
Series target/i386: add a few simple features | expand

Commit Message

Paolo Bonzini June 18, 2023, 9:51 p.m. UTC
TCG supports both 32-bit and 64-bit SYSCALL, so expose it
with "-cpu max" even for 32-bit emulators.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Richard Henderson June 19, 2023, 7:28 a.m. UTC | #1
On 6/18/23 23:51, Paolo Bonzini wrote:
> TCG supports both 32-bit and 64-bit SYSCALL, so expose it
> with "-cpu max" even for 32-bit emulators.
> 
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
>   target/i386/cpu.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
Paolo Bonzini June 19, 2023, 1:49 p.m. UTC | #2
Il dom 18 giu 2023, 23:51 Paolo Bonzini <pbonzini@redhat.com> ha scritto:

> TCG supports both 32-bit and 64-bit SYSCALL, so expose it
> with "-cpu max" even for 32-bit emulators.
>

Nope, this is broken... My bad for assuming that glibc will use syscall if
available—that doesn't happen because the syscall instruction actually is
in the vsyscall page or vDSO.

The fix is still pretty easy, and even SYSENTER could be supported since
after all QEMU *is* exposing the SEP feature when doing user mode
emulation. SYSENTER's design is so hideous though, that in practice no
program will ever use it outside the vDSO/vsyscall page.

Paolo


> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  target/i386/cpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index fc4246223d4..be16c66341d 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -637,7 +637,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t
> vendor1,
>            CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */
>
>  #ifdef TARGET_X86_64
> -#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
> +#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
>  #else
>  #define TCG_EXT2_X86_64_FEATURES 0
>  #endif
> @@ -645,7 +645,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t
> vendor1,
>  #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
>            CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
>            CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
> -          TCG_EXT2_X86_64_FEATURES)
> +          CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES)
>  #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
>            CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
>            CPUID_EXT3_3DNOWPREFETCH)
> --
> 2.40.1
>
>
diff mbox series

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fc4246223d4..be16c66341d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -637,7 +637,7 @@  void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */
 
 #ifdef TARGET_X86_64
-#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
+#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
 #else
 #define TCG_EXT2_X86_64_FEATURES 0
 #endif
@@ -645,7 +645,7 @@  void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
-          TCG_EXT2_X86_64_FEATURES)
+          CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES)
 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
           CPUID_EXT3_3DNOWPREFETCH)