Message ID | 20230615142256.1142849-1-martin@kaiser.cx |
---|---|
State | New |
Headers | show |
Series | [v3] imx_serial: set wake bit when we receive a data byte | expand |
On Thu, 15 Jun 2023 at 15:24, Martin Kaiser <martin@kaiser.cx> wrote: > > The Linux kernel added a flood check for RX data recently in commit > 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This > check uses the wake bit in the UART status register 2. The wake bit > indicates that the receiver detected a start bit on the RX line. If the > kernel sees a number of RX interrupts without the wake bit being set, it > treats this as spurious data and resets the UART port. imx_serial does > never set the wake bit and triggers the kernel's flood check. > > This patch adds support for the wake bit. wake is set when we receive a > new character (it's not set for break events). It seems that wake is > cleared by the kernel driver, the hardware does not have to clear it > automatically after data was read. > > The wake bit can be configured as an interrupt source. Support this > mechanism as well. > > Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Signed-off-by: Martin Kaiser <martin@kaiser.cx> Applied to target-arm.next, thanks. -- PMM
On 19/6/23 12:36, Peter Maydell wrote: > On Thu, 15 Jun 2023 at 15:24, Martin Kaiser <martin@kaiser.cx> wrote: >> >> The Linux kernel added a flood check for RX data recently in commit >> 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This >> check uses the wake bit in the UART status register 2. The wake bit >> indicates that the receiver detected a start bit on the RX line. If the >> kernel sees a number of RX interrupts without the wake bit being set, it >> treats this as spurious data and resets the UART port. imx_serial does >> never set the wake bit and triggers the kernel's flood check. >> >> This patch adds support for the wake bit. wake is set when we receive a >> new character (it's not set for break events). It seems that wake is >> cleared by the kernel driver, the hardware does not have to clear it >> automatically after data was read. >> >> The wake bit can be configured as an interrupt source. Support this >> mechanism as well. >> >> Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> Signed-off-by: Martin Kaiser <martin@kaiser.cx> > > > > Applied to target-arm.next, thanks. > > -- PMM
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index ee1375e26d..1b75a89588 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -80,7 +80,7 @@ static void imx_update(IMXSerialState *s) * TCEN and TXDC are both bit 3 * RDR and DREN are both bit 0 */ - mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN); + mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN); usr2 = s->usr2 & mask; @@ -321,6 +321,9 @@ static void imx_put_data(void *opaque, uint32_t value) static void imx_receive(void *opaque, const uint8_t *buf, int size) { + IMXSerialState *s = (IMXSerialState *)opaque; + + s->usr2 |= USR2_WAKE; imx_put_data(opaque, *buf); } diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index 91c9894ad5..b823f94519 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -71,6 +71,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ +#define UCR4_WKEN BIT(7) /* WAKE interrupt enable */ #define UTS1_TXEMPTY (1<<6) #define UTS1_RXEMPTY (1<<5)