| Message ID | 20230515160201.394587-1-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4] target/ppc: Add POWER9 DD2.2 model | expand |
On 15/05/2023 18:02, Nicholas Piggin wrote: > POWER9 DD2.1 and earlier had significant limitations when running KVM, > including lack of "mixed mode" MMU support (ability to run HPT and RPT > mode on threads of the same core), and a translation prefetch issue > which is worked around by disabling "AIL" mode for the guest. > > These processors are not widely available, and it's difficult to deal > with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU > and make it the default POWER9 CPU. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Which makes me wonder if the P9 DD1 and P10 DD1 cpu definitions are worth keeping, since we don't really try emulating the differences and we don't support them in firmware/skiboot. The only place where we seem to bother is in target/ppc/kvm.c and that's precisely what this patch is trying to avoid. Fred > This is unchanged since v3, just reposting. > > Thanks, > Nick > > hw/ppc/pnv.c | 2 +- > hw/ppc/pnv_core.c | 2 +- > hw/ppc/spapr.c | 2 +- > hw/ppc/spapr_cpu_core.c | 1 + > include/hw/ppc/pnv.h | 2 +- > target/ppc/cpu-models.c | 4 +++- > target/ppc/cpu-models.h | 1 + > target/ppc/cpu_init.c | 21 +++++++++++++++++++-- > tests/qtest/device-plug-test.c | 4 ++-- > 9 files changed, 30 insertions(+), 9 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 11cb48af2f..590fc64b32 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -2171,7 +2171,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) > }; > > mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); > compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); > > xfc->match_nvt = pnv_match_nvt; > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 410f31bdf8..0bc3ad41c8 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -348,7 +348,7 @@ static const TypeInfo pnv_core_infos[] = { > DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), > DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), > DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), > - DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), > + DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), > DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), > }; > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index ddc9c7b1a1..b58e69afd7 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -4631,7 +4631,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) > > smc->dr_lmb_enabled = true; > smc->update_dt_enabled = true; > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); > mc->has_hotpluggable_cpus = true; > mc->nvdimm_supported = true; > smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index 8a4861f45a..9b88dd549a 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -390,6 +390,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { > DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), > + DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), > #ifdef CONFIG_KVM > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 409f3bf763..7e5fef7c43 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -48,7 +48,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, > DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, > TYPE_PNV_CHIP_POWER8NVL) > > -#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") > +#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2") > DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, > TYPE_PNV_CHIP_POWER9) > > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c > index 912b037c63..7dbb47de64 100644 > --- a/target/ppc/cpu-models.c > +++ b/target/ppc/cpu-models.c > @@ -732,6 +732,8 @@ > "POWER9 v1.0") > POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9, > "POWER9 v2.0") > + POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9, > + "POWER9 v2.2") > POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10, > "POWER10 v1.0") > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, > @@ -907,7 +909,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { > { "power8e", "power8e_v2.1" }, > { "power8", "power8_v2.0" }, > { "power8nvl", "power8nvl_v1.0" }, > - { "power9", "power9_v2.0" }, > + { "power9", "power9_v2.2" }, > { "power10", "power10_v2.0" }, > #endif > > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index a77e036b3a..572b5e553a 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -350,6 +350,7 @@ enum { > CPU_POWERPC_POWER9_BASE = 0x004E0000, > CPU_POWERPC_POWER9_DD1 = 0x004E1100, > CPU_POWERPC_POWER9_DD20 = 0x004E1200, > + CPU_POWERPC_POWER9_DD22 = 0x004E1202, > CPU_POWERPC_POWER10_BASE = 0x00800000, > CPU_POWERPC_POWER10_DD1 = 0x00801100, > CPU_POWERPC_POWER10_DD20 = 0x00801200, > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 0ce2e3c91d..6775828dfc 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6284,9 +6284,26 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > return false; > } > > - if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { > - /* Major DD version matches to power9_v1.0 and power9_v2.0 */ > + if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { > + /* Major DD version does not match */ > + return false; > + } > + > + if ((pvr & 0x0f00) == 0x100) { > + /* DD1.x always matches power9_v1.0 */ > return true; > + } else if ((pvr & 0x0f00) == 0x200) { > + if ((pvr & 0xf) < 2) { > + /* DD2.0, DD2.1 match power9_v2.0 */ > + if ((pcc->pvr & 0xf) == 0) { > + return true; > + } > + } else { > + /* DD2.2, DD2.3 match power9_v2.2 */ > + if ((pcc->pvr & 0xf) == 2) { > + return true; > + } > + } > } > > return false; > diff --git a/tests/qtest/device-plug-test.c b/tests/qtest/device-plug-test.c > index 01cecd6e20..165ca13f8c 100644 > --- a/tests/qtest/device-plug-test.c > +++ b/tests/qtest/device-plug-test.c > @@ -168,8 +168,8 @@ static void test_spapr_cpu_unplug_request(void) > { > QTestState *qtest; > > - qtest = qtest_initf("-cpu power9_v2.0 -smp 1,maxcpus=2 " > - "-device power9_v2.0-spapr-cpu-core,core-id=1,id=dev0"); > + qtest = qtest_initf("-cpu power9_v2.2 -smp 1,maxcpus=2 " > + "-device power9_v2.2-spapr-cpu-core,core-id=1,id=dev0"); > > /* similar to test_pci_unplug_request */ > process_device_remove(qtest, "dev0");
On 15/05/2023 18:02, Nicholas Piggin wrote: > POWER9 DD2.1 and earlier had significant limitations when running KVM, > including lack of "mixed mode" MMU support (ability to run HPT and RPT > mode on threads of the same core), and a translation prefetch issue > which is worked around by disabling "AIL" mode for the guest. > > These processors are not widely available, and it's difficult to deal > with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU > and make it the default POWER9 CPU. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- I almost forgot: the patch doesn't apply cleanly on latest upstream. Fred > This is unchanged since v3, just reposting. > > Thanks, > Nick > > hw/ppc/pnv.c | 2 +- > hw/ppc/pnv_core.c | 2 +- > hw/ppc/spapr.c | 2 +- > hw/ppc/spapr_cpu_core.c | 1 + > include/hw/ppc/pnv.h | 2 +- > target/ppc/cpu-models.c | 4 +++- > target/ppc/cpu-models.h | 1 + > target/ppc/cpu_init.c | 21 +++++++++++++++++++-- > tests/qtest/device-plug-test.c | 4 ++-- > 9 files changed, 30 insertions(+), 9 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 11cb48af2f..590fc64b32 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -2171,7 +2171,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) > }; > > mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); > compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); > > xfc->match_nvt = pnv_match_nvt; > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 410f31bdf8..0bc3ad41c8 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -348,7 +348,7 @@ static const TypeInfo pnv_core_infos[] = { > DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), > DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), > DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), > - DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), > + DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), > DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), > }; > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index ddc9c7b1a1..b58e69afd7 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -4631,7 +4631,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) > > smc->dr_lmb_enabled = true; > smc->update_dt_enabled = true; > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); > mc->has_hotpluggable_cpus = true; > mc->nvdimm_supported = true; > smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index 8a4861f45a..9b88dd549a 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -390,6 +390,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { > DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), > + DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), > #ifdef CONFIG_KVM > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 409f3bf763..7e5fef7c43 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -48,7 +48,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, > DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, > TYPE_PNV_CHIP_POWER8NVL) > > -#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") > +#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2") > DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, > TYPE_PNV_CHIP_POWER9) > > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c > index 912b037c63..7dbb47de64 100644 > --- a/target/ppc/cpu-models.c > +++ b/target/ppc/cpu-models.c > @@ -732,6 +732,8 @@ > "POWER9 v1.0") > POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9, > "POWER9 v2.0") > + POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9, > + "POWER9 v2.2") > POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10, > "POWER10 v1.0") > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, > @@ -907,7 +909,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { > { "power8e", "power8e_v2.1" }, > { "power8", "power8_v2.0" }, > { "power8nvl", "power8nvl_v1.0" }, > - { "power9", "power9_v2.0" }, > + { "power9", "power9_v2.2" }, > { "power10", "power10_v2.0" }, > #endif > > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index a77e036b3a..572b5e553a 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -350,6 +350,7 @@ enum { > CPU_POWERPC_POWER9_BASE = 0x004E0000, > CPU_POWERPC_POWER9_DD1 = 0x004E1100, > CPU_POWERPC_POWER9_DD20 = 0x004E1200, > + CPU_POWERPC_POWER9_DD22 = 0x004E1202, > CPU_POWERPC_POWER10_BASE = 0x00800000, > CPU_POWERPC_POWER10_DD1 = 0x00801100, > CPU_POWERPC_POWER10_DD20 = 0x00801200, > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 0ce2e3c91d..6775828dfc 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6284,9 +6284,26 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > return false; > } > > - if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { > - /* Major DD version matches to power9_v1.0 and power9_v2.0 */ > + if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { > + /* Major DD version does not match */ > + return false; > + } > + > + if ((pvr & 0x0f00) == 0x100) { > + /* DD1.x always matches power9_v1.0 */ > return true; > + } else if ((pvr & 0x0f00) == 0x200) { > + if ((pvr & 0xf) < 2) { > + /* DD2.0, DD2.1 match power9_v2.0 */ > + if ((pcc->pvr & 0xf) == 0) { > + return true; > + } > + } else { > + /* DD2.2, DD2.3 match power9_v2.2 */ > + if ((pcc->pvr & 0xf) == 2) { > + return true; > + } > + } > } > > return false; > diff --git a/tests/qtest/device-plug-test.c b/tests/qtest/device-plug-test.c > index 01cecd6e20..165ca13f8c 100644 > --- a/tests/qtest/device-plug-test.c > +++ b/tests/qtest/device-plug-test.c > @@ -168,8 +168,8 @@ static void test_spapr_cpu_unplug_request(void) > { > QTestState *qtest; > > - qtest = qtest_initf("-cpu power9_v2.0 -smp 1,maxcpus=2 " > - "-device power9_v2.0-spapr-cpu-core,core-id=1,id=dev0"); > + qtest = qtest_initf("-cpu power9_v2.2 -smp 1,maxcpus=2 " > + "-device power9_v2.2-spapr-cpu-core,core-id=1,id=dev0"); > > /* similar to test_pci_unplug_request */ > process_device_remove(qtest, "dev0");
On 5/15/23 18:02, Nicholas Piggin wrote: > POWER9 DD2.1 and earlier had significant limitations when running KVM, > including lack of "mixed mode" MMU support (ability to run HPT and RPT > mode on threads of the same core), and a translation prefetch issue > which is worked around by disabling "AIL" mode for the guest. > > These processors are not widely available, and it's difficult to deal > with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU > and make it the default POWER9 CPU. I would remove power9_v1.0 and power9_v2.0 (not shipped AFAIK) and maybe add power9_v2.3 since it has a little more features. It can be done as a followup. Thanks, C. > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- > This is unchanged since v3, just reposting. > > Thanks, > Nick > > hw/ppc/pnv.c | 2 +- > hw/ppc/pnv_core.c | 2 +- > hw/ppc/spapr.c | 2 +- > hw/ppc/spapr_cpu_core.c | 1 + > include/hw/ppc/pnv.h | 2 +- > target/ppc/cpu-models.c | 4 +++- > target/ppc/cpu-models.h | 1 + > target/ppc/cpu_init.c | 21 +++++++++++++++++++-- > tests/qtest/device-plug-test.c | 4 ++-- > 9 files changed, 30 insertions(+), 9 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 11cb48af2f..590fc64b32 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -2171,7 +2171,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) > }; > > mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); > compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); > > xfc->match_nvt = pnv_match_nvt; > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 410f31bdf8..0bc3ad41c8 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -348,7 +348,7 @@ static const TypeInfo pnv_core_infos[] = { > DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), > DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), > DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), > - DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), > + DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), > DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), > }; > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index ddc9c7b1a1..b58e69afd7 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -4631,7 +4631,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) > > smc->dr_lmb_enabled = true; > smc->update_dt_enabled = true; > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); > mc->has_hotpluggable_cpus = true; > mc->nvdimm_supported = true; > smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index 8a4861f45a..9b88dd549a 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -390,6 +390,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { > DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), > + DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), > #ifdef CONFIG_KVM > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 409f3bf763..7e5fef7c43 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -48,7 +48,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, > DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, > TYPE_PNV_CHIP_POWER8NVL) > > -#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") > +#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2") > DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, > TYPE_PNV_CHIP_POWER9) > > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c > index 912b037c63..7dbb47de64 100644 > --- a/target/ppc/cpu-models.c > +++ b/target/ppc/cpu-models.c > @@ -732,6 +732,8 @@ > "POWER9 v1.0") > POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9, > "POWER9 v2.0") > + POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9, > + "POWER9 v2.2") > POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10, > "POWER10 v1.0") > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, > @@ -907,7 +909,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { > { "power8e", "power8e_v2.1" }, > { "power8", "power8_v2.0" }, > { "power8nvl", "power8nvl_v1.0" }, > - { "power9", "power9_v2.0" }, > + { "power9", "power9_v2.2" }, > { "power10", "power10_v2.0" }, > #endif > > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index a77e036b3a..572b5e553a 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -350,6 +350,7 @@ enum { > CPU_POWERPC_POWER9_BASE = 0x004E0000, > CPU_POWERPC_POWER9_DD1 = 0x004E1100, > CPU_POWERPC_POWER9_DD20 = 0x004E1200, > + CPU_POWERPC_POWER9_DD22 = 0x004E1202, > CPU_POWERPC_POWER10_BASE = 0x00800000, > CPU_POWERPC_POWER10_DD1 = 0x00801100, > CPU_POWERPC_POWER10_DD20 = 0x00801200, > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 0ce2e3c91d..6775828dfc 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6284,9 +6284,26 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > return false; > } > > - if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { > - /* Major DD version matches to power9_v1.0 and power9_v2.0 */ > + if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { > + /* Major DD version does not match */ > + return false; > + } > + > + if ((pvr & 0x0f00) == 0x100) { > + /* DD1.x always matches power9_v1.0 */ > return true; > + } else if ((pvr & 0x0f00) == 0x200) { > + if ((pvr & 0xf) < 2) { > + /* DD2.0, DD2.1 match power9_v2.0 */ > + if ((pcc->pvr & 0xf) == 0) { > + return true; > + } > + } else { > + /* DD2.2, DD2.3 match power9_v2.2 */ > + if ((pcc->pvr & 0xf) == 2) { > + return true; > + } > + } > } > > return false; > diff --git a/tests/qtest/device-plug-test.c b/tests/qtest/device-plug-test.c > index 01cecd6e20..165ca13f8c 100644 > --- a/tests/qtest/device-plug-test.c > +++ b/tests/qtest/device-plug-test.c > @@ -168,8 +168,8 @@ static void test_spapr_cpu_unplug_request(void) > { > QTestState *qtest; > > - qtest = qtest_initf("-cpu power9_v2.0 -smp 1,maxcpus=2 " > - "-device power9_v2.0-spapr-cpu-core,core-id=1,id=dev0"); > + qtest = qtest_initf("-cpu power9_v2.2 -smp 1,maxcpus=2 " > + "-device power9_v2.2-spapr-cpu-core,core-id=1,id=dev0"); > > /* similar to test_pci_unplug_request */ > process_device_remove(qtest, "dev0");
<correcting my email in CC> On 5/15/23 21:32, Nicholas Piggin wrote: > POWER9 DD2.1 and earlier had significant limitations when running KVM, > including lack of "mixed mode" MMU support (ability to run HPT and RPT > mode on threads of the same core), and a translation prefetch issue > which is worked around by disabling "AIL" mode for the guest. > > These processors are not widely available, and it's difficult to deal > with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU > and make it the default POWER9 CPU. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- > This is unchanged since v3, just reposting. > > Thanks, > Nick > > hw/ppc/pnv.c | 2 +- > hw/ppc/pnv_core.c | 2 +- > hw/ppc/spapr.c | 2 +- > hw/ppc/spapr_cpu_core.c | 1 + > include/hw/ppc/pnv.h | 2 +- > target/ppc/cpu-models.c | 4 +++- > target/ppc/cpu-models.h | 1 + > target/ppc/cpu_init.c | 21 +++++++++++++++++++-- > tests/qtest/device-plug-test.c | 4 ++-- > 9 files changed, 30 insertions(+), 9 deletions(-) > <snip> > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index a77e036b3a..572b5e553a 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -350,6 +350,7 @@ enum { > CPU_POWERPC_POWER9_BASE = 0x004E0000, > CPU_POWERPC_POWER9_DD1 = 0x004E1100, > CPU_POWERPC_POWER9_DD20 = 0x004E1200, > + CPU_POWERPC_POWER9_DD22 = 0x004E1202, > CPU_POWERPC_POWER10_BASE = 0x00800000, > CPU_POWERPC_POWER10_DD1 = 0x00801100, > CPU_POWERPC_POWER10_DD20 = 0x00801200, > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 0ce2e3c91d..6775828dfc 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6284,9 +6284,26 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > return false; > } > > - if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { > - /* Major DD version matches to power9_v1.0 and power9_v2.0 */ > + if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { > + /* Major DD version does not match */ > + return false; > + } > + > + if ((pvr & 0x0f00) == 0x100) { > + /* DD1.x always matches power9_v1.0 */ > return true; > + } else if ((pvr & 0x0f00) == 0x200) { > + if ((pvr & 0xf) < 2) { > + /* DD2.0, DD2.1 match power9_v2.0 */ > + if ((pcc->pvr & 0xf) == 0) { > + return true; > + } > + } else { > + /* DD2.2, DD2.3 match power9_v2.2 */ > + if ((pcc->pvr & 0xf) == 2) { The comment is futuristic about DD2.3 although the condition checks only for DD2.2, may be update comment for now and another patch later along with other changes needed to support 2.3? Otherwise, looks fine to me. Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> regards, Harsh > + return true; > + } > + } > } > > return false; > diff --git a/tests/qtest/device-plug-test.c b/tests/qtest/device-plug-test.c > index 01cecd6e20..165ca13f8c 100644 > --- a/tests/qtest/device-plug-test.c > +++ b/tests/qtest/device-plug-test.c > @@ -168,8 +168,8 @@ static void test_spapr_cpu_unplug_request(void) > { > QTestState *qtest; > > - qtest = qtest_initf("-cpu power9_v2.0 -smp 1,maxcpus=2 " > - "-device power9_v2.0-spapr-cpu-core,core-id=1,id=dev0"); > + qtest = qtest_initf("-cpu power9_v2.2 -smp 1,maxcpus=2 " > + "-device power9_v2.2-spapr-cpu-core,core-id=1,id=dev0"); > > /* similar to test_pci_unplug_request */ > process_device_remove(qtest, "dev0");
On Tue May 16, 2023 at 5:58 PM AEST, Frederic Barrat wrote: > > > On 15/05/2023 18:02, Nicholas Piggin wrote: > > POWER9 DD2.1 and earlier had significant limitations when running KVM, > > including lack of "mixed mode" MMU support (ability to run HPT and RPT > > mode on threads of the same core), and a translation prefetch issue > > which is worked around by disabling "AIL" mode for the guest. > > > > These processors are not widely available, and it's difficult to deal > > with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU > > and make it the default POWER9 CPU. > > > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > > --- > > > I almost forgot: the patch doesn't apply cleanly on latest upstream. Oh, some fuzz due to needing the PVR patch I think. Thanks, Nick
On Tue May 16, 2023 at 5:56 PM AEST, Frederic Barrat wrote: > > > On 15/05/2023 18:02, Nicholas Piggin wrote: > > POWER9 DD2.1 and earlier had significant limitations when running KVM, > > including lack of "mixed mode" MMU support (ability to run HPT and RPT > > mode on threads of the same core), and a translation prefetch issue > > which is worked around by disabling "AIL" mode for the guest. > > > > These processors are not widely available, and it's difficult to deal > > with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU > > and make it the default POWER9 CPU. > > > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > > --- > > Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> > > Which makes me wonder if the P9 DD1 and P10 DD1 cpu definitions are > worth keeping, since we don't really try emulating the differences and > we don't support them in firmware/skiboot. The only place where we seem > to bother is in target/ppc/kvm.c and that's precisely what this patch is > trying to avoid. +1. We could do a follow up as Cedric suggested. Thanks, Nick
On Tue May 16, 2023 at 6:44 PM AEST, Cédric Le Goater wrote: > On 5/15/23 18:02, Nicholas Piggin wrote: > > POWER9 DD2.1 and earlier had significant limitations when running KVM, > > including lack of "mixed mode" MMU support (ability to run HPT and RPT > > mode on threads of the same core), and a translation prefetch issue > > which is worked around by disabling "AIL" mode for the guest. > > > > These processors are not widely available, and it's difficult to deal > > with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU > > and make it the default POWER9 CPU. > > I would remove power9_v1.0 and power9_v2.0 (not shipped AFAIK) and maybe > add power9_v2.3 since it has a little more features. Yes to removing DD1 (and for P10), and adding 2.3. Not sure about removing 2.0, we carry this radix MMU prefetch workaround thing for 2.0 and 2.1 in upstream KVM which causes some of this AIL-3 complication. Having a 2.0 model might help with that, and if it doesn't cause much effort to maintain I'd like to keep it for a bit. Can remove it if upstream KVM drops support or it causes problems. Thanks, Nick
On Tue May 16, 2023 at 7:23 PM AEST, Harsh Prateek Bora wrote: > <correcting my email in CC> > > On 5/15/23 21:32, Nicholas Piggin wrote: > > POWER9 DD2.1 and earlier had significant limitations when running KVM, > > including lack of "mixed mode" MMU support (ability to run HPT and RPT > > mode on threads of the same core), and a translation prefetch issue > > which is worked around by disabling "AIL" mode for the guest. > > > > These processors are not widely available, and it's difficult to deal > > with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU > > and make it the default POWER9 CPU. > > > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > > --- > > This is unchanged since v3, just reposting. > > > > Thanks, > > Nick > > > > hw/ppc/pnv.c | 2 +- > > hw/ppc/pnv_core.c | 2 +- > > hw/ppc/spapr.c | 2 +- > > hw/ppc/spapr_cpu_core.c | 1 + > > include/hw/ppc/pnv.h | 2 +- > > target/ppc/cpu-models.c | 4 +++- > > target/ppc/cpu-models.h | 1 + > > target/ppc/cpu_init.c | 21 +++++++++++++++++++-- > > tests/qtest/device-plug-test.c | 4 ++-- > > 9 files changed, 30 insertions(+), 9 deletions(-) > > > > <snip> > > > > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > > index a77e036b3a..572b5e553a 100644 > > --- a/target/ppc/cpu-models.h > > +++ b/target/ppc/cpu-models.h > > @@ -350,6 +350,7 @@ enum { > > CPU_POWERPC_POWER9_BASE = 0x004E0000, > > CPU_POWERPC_POWER9_DD1 = 0x004E1100, > > CPU_POWERPC_POWER9_DD20 = 0x004E1200, > > + CPU_POWERPC_POWER9_DD22 = 0x004E1202, > > CPU_POWERPC_POWER10_BASE = 0x00800000, > > CPU_POWERPC_POWER10_DD1 = 0x00801100, > > CPU_POWERPC_POWER10_DD20 = 0x00801200, > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > > index 0ce2e3c91d..6775828dfc 100644 > > --- a/target/ppc/cpu_init.c > > +++ b/target/ppc/cpu_init.c > > @@ -6284,9 +6284,26 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > > return false; > > } > > > > - if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { > > - /* Major DD version matches to power9_v1.0 and power9_v2.0 */ > > + if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { > > + /* Major DD version does not match */ > > + return false; > > + } > > + > > + if ((pvr & 0x0f00) == 0x100) { > > + /* DD1.x always matches power9_v1.0 */ > > return true; > > + } else if ((pvr & 0x0f00) == 0x200) { > > + if ((pvr & 0xf) < 2) { > > + /* DD2.0, DD2.1 match power9_v2.0 */ > > + if ((pcc->pvr & 0xf) == 0) { > > + return true; > > + } > > + } else { > > + /* DD2.2, DD2.3 match power9_v2.2 */ > > + if ((pcc->pvr & 0xf) == 2) { > The comment is futuristic about DD2.3 although the condition checks only > for DD2.2, may be update comment for now and another patch later along > with other changes needed to support 2.3? In the case of KVM, PVR matching code matches 'pvr' from the host to the best pcc. So the comment matches the code. It's just a bit clunky. But as Cedric said we might want a 2.3 type as well if we want to account for the nuances in better detail. No objection to adding it. Thanks, Nick
On 5/15/23 13:02, Nicholas Piggin wrote: > POWER9 DD2.1 and earlier had significant limitations when running KVM, > including lack of "mixed mode" MMU support (ability to run HPT and RPT > mode on threads of the same core), and a translation prefetch issue > which is worked around by disabling "AIL" mode for the guest. > > These processors are not widely available, and it's difficult to deal > with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU > and make it the default POWER9 CPU. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- Patch applied cleanly on top of ppc-next so I'm queueing it. Any comments/improvements based on DD2.3 support can be done in a follow-up. Thanks, Daniel > This is unchanged since v3, just reposting. > > Thanks, > Nick > > hw/ppc/pnv.c | 2 +- > hw/ppc/pnv_core.c | 2 +- > hw/ppc/spapr.c | 2 +- > hw/ppc/spapr_cpu_core.c | 1 + > include/hw/ppc/pnv.h | 2 +- > target/ppc/cpu-models.c | 4 +++- > target/ppc/cpu-models.h | 1 + > target/ppc/cpu_init.c | 21 +++++++++++++++++++-- > tests/qtest/device-plug-test.c | 4 ++-- > 9 files changed, 30 insertions(+), 9 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 11cb48af2f..590fc64b32 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -2171,7 +2171,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) > }; > > mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); > compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); > > xfc->match_nvt = pnv_match_nvt; > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 410f31bdf8..0bc3ad41c8 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -348,7 +348,7 @@ static const TypeInfo pnv_core_infos[] = { > DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), > DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), > DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), > - DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), > + DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), > DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), > }; > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index ddc9c7b1a1..b58e69afd7 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -4631,7 +4631,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) > > smc->dr_lmb_enabled = true; > smc->update_dt_enabled = true; > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); > mc->has_hotpluggable_cpus = true; > mc->nvdimm_supported = true; > smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index 8a4861f45a..9b88dd549a 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -390,6 +390,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { > DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), > + DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), > #ifdef CONFIG_KVM > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 409f3bf763..7e5fef7c43 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -48,7 +48,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, > DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, > TYPE_PNV_CHIP_POWER8NVL) > > -#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") > +#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2") > DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, > TYPE_PNV_CHIP_POWER9) > > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c > index 912b037c63..7dbb47de64 100644 > --- a/target/ppc/cpu-models.c > +++ b/target/ppc/cpu-models.c > @@ -732,6 +732,8 @@ > "POWER9 v1.0") > POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9, > "POWER9 v2.0") > + POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9, > + "POWER9 v2.2") > POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10, > "POWER10 v1.0") > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, > @@ -907,7 +909,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { > { "power8e", "power8e_v2.1" }, > { "power8", "power8_v2.0" }, > { "power8nvl", "power8nvl_v1.0" }, > - { "power9", "power9_v2.0" }, > + { "power9", "power9_v2.2" }, > { "power10", "power10_v2.0" }, > #endif > > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index a77e036b3a..572b5e553a 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -350,6 +350,7 @@ enum { > CPU_POWERPC_POWER9_BASE = 0x004E0000, > CPU_POWERPC_POWER9_DD1 = 0x004E1100, > CPU_POWERPC_POWER9_DD20 = 0x004E1200, > + CPU_POWERPC_POWER9_DD22 = 0x004E1202, > CPU_POWERPC_POWER10_BASE = 0x00800000, > CPU_POWERPC_POWER10_DD1 = 0x00801100, > CPU_POWERPC_POWER10_DD20 = 0x00801200, > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 0ce2e3c91d..6775828dfc 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6284,9 +6284,26 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > return false; > } > > - if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { > - /* Major DD version matches to power9_v1.0 and power9_v2.0 */ > + if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { > + /* Major DD version does not match */ > + return false; > + } > + > + if ((pvr & 0x0f00) == 0x100) { > + /* DD1.x always matches power9_v1.0 */ > return true; > + } else if ((pvr & 0x0f00) == 0x200) { > + if ((pvr & 0xf) < 2) { > + /* DD2.0, DD2.1 match power9_v2.0 */ > + if ((pcc->pvr & 0xf) == 0) { > + return true; > + } > + } else { > + /* DD2.2, DD2.3 match power9_v2.2 */ > + if ((pcc->pvr & 0xf) == 2) { > + return true; > + } > + } > } > > return false; > diff --git a/tests/qtest/device-plug-test.c b/tests/qtest/device-plug-test.c > index 01cecd6e20..165ca13f8c 100644 > --- a/tests/qtest/device-plug-test.c > +++ b/tests/qtest/device-plug-test.c > @@ -168,8 +168,8 @@ static void test_spapr_cpu_unplug_request(void) > { > QTestState *qtest; > > - qtest = qtest_initf("-cpu power9_v2.0 -smp 1,maxcpus=2 " > - "-device power9_v2.0-spapr-cpu-core,core-id=1,id=dev0"); > + qtest = qtest_initf("-cpu power9_v2.2 -smp 1,maxcpus=2 " > + "-device power9_v2.2-spapr-cpu-core,core-id=1,id=dev0"); > > /* similar to test_pci_unplug_request */ > process_device_remove(qtest, "dev0");
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 11cb48af2f..590fc64b32 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2171,7 +2171,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) }; mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); xfc->match_nvt = pnv_match_nvt; diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 410f31bdf8..0bc3ad41c8 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -348,7 +348,7 @@ static const TypeInfo pnv_core_infos[] = { DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), - DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), + DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), }; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index ddc9c7b1a1..b58e69afd7 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4631,7 +4631,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) smc->dr_lmb_enabled = true; smc->update_dt_enabled = true; - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); mc->has_hotpluggable_cpus = true; mc->nvdimm_supported = true; smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 8a4861f45a..9b88dd549a 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -390,6 +390,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), + DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), #ifdef CONFIG_KVM diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 409f3bf763..7e5fef7c43 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -48,7 +48,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, TYPE_PNV_CHIP_POWER8NVL) -#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") +#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2") DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, TYPE_PNV_CHIP_POWER9) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 912b037c63..7dbb47de64 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -732,6 +732,8 @@ "POWER9 v1.0") POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9, "POWER9 v2.0") + POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9, + "POWER9 v2.2") POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10, "POWER10 v1.0") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, @@ -907,7 +909,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { { "power8e", "power8e_v2.1" }, { "power8", "power8_v2.0" }, { "power8nvl", "power8nvl_v1.0" }, - { "power9", "power9_v2.0" }, + { "power9", "power9_v2.2" }, { "power10", "power10_v2.0" }, #endif diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index a77e036b3a..572b5e553a 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -350,6 +350,7 @@ enum { CPU_POWERPC_POWER9_BASE = 0x004E0000, CPU_POWERPC_POWER9_DD1 = 0x004E1100, CPU_POWERPC_POWER9_DD20 = 0x004E1200, + CPU_POWERPC_POWER9_DD22 = 0x004E1202, CPU_POWERPC_POWER10_BASE = 0x00800000, CPU_POWERPC_POWER10_DD1 = 0x00801100, CPU_POWERPC_POWER10_DD20 = 0x00801200, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 0ce2e3c91d..6775828dfc 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6284,9 +6284,26 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) return false; } - if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { - /* Major DD version matches to power9_v1.0 and power9_v2.0 */ + if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { + /* Major DD version does not match */ + return false; + } + + if ((pvr & 0x0f00) == 0x100) { + /* DD1.x always matches power9_v1.0 */ return true; + } else if ((pvr & 0x0f00) == 0x200) { + if ((pvr & 0xf) < 2) { + /* DD2.0, DD2.1 match power9_v2.0 */ + if ((pcc->pvr & 0xf) == 0) { + return true; + } + } else { + /* DD2.2, DD2.3 match power9_v2.2 */ + if ((pcc->pvr & 0xf) == 2) { + return true; + } + } } return false; diff --git a/tests/qtest/device-plug-test.c b/tests/qtest/device-plug-test.c index 01cecd6e20..165ca13f8c 100644 --- a/tests/qtest/device-plug-test.c +++ b/tests/qtest/device-plug-test.c @@ -168,8 +168,8 @@ static void test_spapr_cpu_unplug_request(void) { QTestState *qtest; - qtest = qtest_initf("-cpu power9_v2.0 -smp 1,maxcpus=2 " - "-device power9_v2.0-spapr-cpu-core,core-id=1,id=dev0"); + qtest = qtest_initf("-cpu power9_v2.2 -smp 1,maxcpus=2 " + "-device power9_v2.2-spapr-cpu-core,core-id=1,id=dev0"); /* similar to test_pci_unplug_request */ process_device_remove(qtest, "dev0");
POWER9 DD2.1 and earlier had significant limitations when running KVM, including lack of "mixed mode" MMU support (ability to run HPT and RPT mode on threads of the same core), and a translation prefetch issue which is worked around by disabling "AIL" mode for the guest. These processors are not widely available, and it's difficult to deal with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU and make it the default POWER9 CPU. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- This is unchanged since v3, just reposting. Thanks, Nick hw/ppc/pnv.c | 2 +- hw/ppc/pnv_core.c | 2 +- hw/ppc/spapr.c | 2 +- hw/ppc/spapr_cpu_core.c | 1 + include/hw/ppc/pnv.h | 2 +- target/ppc/cpu-models.c | 4 +++- target/ppc/cpu-models.h | 1 + target/ppc/cpu_init.c | 21 +++++++++++++++++++-- tests/qtest/device-plug-test.c | 4 ++-- 9 files changed, 30 insertions(+), 9 deletions(-)