Message ID | 20220801171843.72986-3-mchitale@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | RISC-V Smstateen support | expand |
在 2022/8/2 上午1:18, Mayuresh Chitale 写道: > Accesses to henvcfg, henvcfgh and senvcfg are allowed only if > corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an > illegal instruction trap is generated. > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > --- > roms/opensbi | 2 +- > target/riscv/csr.c | 83 ++++++++++++++++++++++++++++++++++++++++++---- > 2 files changed, 77 insertions(+), 8 deletions(-) > > diff --git a/roms/opensbi b/roms/opensbi > index 4489876e93..48f91ee9c9 160000 > --- a/roms/opensbi > +++ b/roms/opensbi > @@ -1 +1 @@ > -Subproject commit 4489876e933d8ba0d8bc6c64bae71e295d45faac > +Subproject commit 48f91ee9c960f048c4a7d1da4447d31e04931e38 > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index ad1642fb9b..011d6c5976 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -40,6 +40,38 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) > } > > /* Predicates */ > +#if !defined(CONFIG_USER_ONLY) > +static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, > + uint64_t bit) > +{ > + bool virt = riscv_cpu_virt_enabled(env); > + CPUState *cs = env_cpu(env); > + RISCVCPU *cpu = RISCV_CPU(cs); > + > + if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) { > + return RISCV_EXCP_NONE; > + } > + > + if (!(env->mstateen[index] & bit)) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + if (virt) { > + if (!(env->hstateen[index] & bit)) { > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > + } > + } > + > + if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { > + if (!(env->sstateen[index] & bit)) { > + return RISCV_EXCP_ILLEGAL_INST; > + } VU mode seems not be taken into consideration. For VU mode, the exception will be RISCV_EXCP_VIRT_INSTRUCTION_FAULT instead if "!(env->sstateen[index] & bit)" here. Regards, Weiwei Li > + } > + > + return RISCV_EXCP_NONE; > +} > +#endif > + > static RISCVException fs(CPURISCVState *env, int csrno) > { > #if !defined(CONFIG_USER_ONLY) > @@ -1715,6 +1747,13 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > static RISCVException read_senvcfg(CPURISCVState *env, int csrno, > target_ulong *val) > { > + RISCVException ret; > + > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > + if (ret != RISCV_EXCP_NONE) { > + return ret; > + } > + > *val = env->senvcfg; > return RISCV_EXCP_NONE; > } > @@ -1723,15 +1762,27 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > target_ulong val) > { > uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; > + RISCVException ret; > > - env->senvcfg = (env->senvcfg & ~mask) | (val & mask); > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > + if (ret != RISCV_EXCP_NONE) { > + return ret; > + } > > + env->senvcfg = (env->senvcfg & ~mask) | (val & mask); > return RISCV_EXCP_NONE; > } > > static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > target_ulong *val) > { > + RISCVException ret; > + > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > + if (ret != RISCV_EXCP_NONE) { > + return ret; > + } > + > *val = env->henvcfg; > return RISCV_EXCP_NONE; > } > @@ -1740,6 +1791,12 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > target_ulong val) > { > uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; > + RISCVException ret; > + > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > + if (ret != RISCV_EXCP_NONE) { > + return ret; > + } > > if (riscv_cpu_mxl(env) == MXL_RV64) { > mask |= HENVCFG_PBMTE | HENVCFG_STCE; > @@ -1753,6 +1810,13 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > target_ulong *val) > { > + RISCVException ret; > + > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > + if (ret != RISCV_EXCP_NONE) { > + return ret; > + } > + > *val = env->henvcfg >> 32; > return RISCV_EXCP_NONE; > } > @@ -1762,9 +1826,14 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > { > uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; > uint64_t valh = (uint64_t)val << 32; > + RISCVException ret; > > - env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > + if (ret != RISCV_EXCP_NONE) { > + return ret; > + } > > + env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); > return RISCV_EXCP_NONE; > } > > @@ -1796,7 +1865,7 @@ static RISCVException write_mstateen(CPURISCVState *env, int csrno, > static RISCVException write_mstateen0(CPURISCVState *env, int csrno, > target_ulong new_val) > { > - uint64_t wr_mask = SMSTATEEN_STATEEN; > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > return write_mstateen(env, csrno, wr_mask, new_val); > } > @@ -1843,7 +1912,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno, > static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, > target_ulong new_val) > { > - uint64_t wr_mask = SMSTATEEN_STATEEN; > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > return write_mstateenh(env, csrno, wr_mask, new_val); > } > @@ -1892,7 +1961,7 @@ static RISCVException write_hstateen(CPURISCVState *env, int csrno, > static RISCVException write_hstateen0(CPURISCVState *env, int csrno, > target_ulong new_val) > { > - uint64_t wr_mask = SMSTATEEN_STATEEN; > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > return write_hstateen(env, csrno, wr_mask, new_val); > } > @@ -1943,7 +2012,7 @@ static RISCVException write_hstateenh(CPURISCVState *env, int csrno, > static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, > target_ulong new_val) > { > - uint64_t wr_mask = SMSTATEEN_STATEEN; > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > return write_hstateenh(env, csrno, wr_mask, new_val); > } > @@ -2002,7 +2071,7 @@ static RISCVException write_sstateen(CPURISCVState *env, int csrno, > static RISCVException write_sstateen0(CPURISCVState *env, int csrno, > target_ulong new_val) > { > - uint64_t wr_mask = SMSTATEEN_STATEEN; > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > return write_sstateen(env, csrno, wr_mask, new_val); > }
On Wed, 2022-08-03 at 16:24 +0800, Weiwei Li wrote: > 在 2022/8/2 上午1:18, Mayuresh Chitale 写道: > > Accesses to henvcfg, henvcfgh and senvcfg are allowed only if > > corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an > > illegal instruction trap is generated. > > > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > > --- > > roms/opensbi | 2 +- > > target/riscv/csr.c | 83 > > ++++++++++++++++++++++++++++++++++++++++++---- > > 2 files changed, 77 insertions(+), 8 deletions(-) > > > > diff --git a/roms/opensbi b/roms/opensbi > > index 4489876e93..48f91ee9c9 160000 > > --- a/roms/opensbi > > +++ b/roms/opensbi > > @@ -1 +1 @@ > > -Subproject commit 4489876e933d8ba0d8bc6c64bae71e295d45faac > > +Subproject commit 48f91ee9c960f048c4a7d1da4447d31e04931e38 > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index ad1642fb9b..011d6c5976 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -40,6 +40,38 @@ void riscv_set_csr_ops(int csrno, > > riscv_csr_operations *ops) > > } > > > > /* Predicates */ > > +#if !defined(CONFIG_USER_ONLY) > > +static RISCVException smstateen_acc_ok(CPURISCVState *env, int > > index, > > + uint64_t bit) > > +{ > > + bool virt = riscv_cpu_virt_enabled(env); > > + CPUState *cs = env_cpu(env); > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + > > + if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) { > > + return RISCV_EXCP_NONE; > > + } > > + > > + if (!(env->mstateen[index] & bit)) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + if (virt) { > > + if (!(env->hstateen[index] & bit)) { > > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > > + } > > + } > > + > > + if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { > > + if (!(env->sstateen[index] & bit)) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > VU mode seems not be taken into consideration. For VU mode, the > exception will be > > RISCV_EXCP_VIRT_INSTRUCTION_FAULT instead if "!(env->sstateen[index] > & bit)" here. Ok. I will fix it in the next version. > > > Regards, > > Weiwei Li > > > + } > > + > > + return RISCV_EXCP_NONE; > > +} > > +#endif > > + > > static RISCVException fs(CPURISCVState *env, int csrno) > > { > > #if !defined(CONFIG_USER_ONLY) > > @@ -1715,6 +1747,13 @@ static RISCVException > > write_menvcfgh(CPURISCVState *env, int csrno, > > static RISCVException read_senvcfg(CPURISCVState *env, int csrno, > > target_ulong *val) > > { > > + RISCVException ret; > > + > > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > > + if (ret != RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > *val = env->senvcfg; > > return RISCV_EXCP_NONE; > > } > > @@ -1723,15 +1762,27 @@ static RISCVException > > write_senvcfg(CPURISCVState *env, int csrno, > > target_ulong val) > > { > > uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | > > SENVCFG_CBZE; > > + RISCVException ret; > > > > - env->senvcfg = (env->senvcfg & ~mask) | (val & mask); > > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > > + if (ret != RISCV_EXCP_NONE) { > > + return ret; > > + } > > > > + env->senvcfg = (env->senvcfg & ~mask) | (val & mask); > > return RISCV_EXCP_NONE; > > } > > > > static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > > target_ulong *val) > > { > > + RISCVException ret; > > + > > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > > + if (ret != RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > *val = env->henvcfg; > > return RISCV_EXCP_NONE; > > } > > @@ -1740,6 +1791,12 @@ static RISCVException > > write_henvcfg(CPURISCVState *env, int csrno, > > target_ulong val) > > { > > uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | > > HENVCFG_CBZE; > > + RISCVException ret; > > + > > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > > + if (ret != RISCV_EXCP_NONE) { > > + return ret; > > + } > > > > if (riscv_cpu_mxl(env) == MXL_RV64) { > > mask |= HENVCFG_PBMTE | HENVCFG_STCE; > > @@ -1753,6 +1810,13 @@ static RISCVException > > write_henvcfg(CPURISCVState *env, int csrno, > > static RISCVException read_henvcfgh(CPURISCVState *env, int > > csrno, > > target_ulong *val) > > { > > + RISCVException ret; > > + > > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > > + if (ret != RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > *val = env->henvcfg >> 32; > > return RISCV_EXCP_NONE; > > } > > @@ -1762,9 +1826,14 @@ static RISCVException > > write_henvcfgh(CPURISCVState *env, int csrno, > > { > > uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; > > uint64_t valh = (uint64_t)val << 32; > > + RISCVException ret; > > > > - env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); > > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > > + if (ret != RISCV_EXCP_NONE) { > > + return ret; > > + } > > > > + env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); > > return RISCV_EXCP_NONE; > > } > > > > @@ -1796,7 +1865,7 @@ static RISCVException > > write_mstateen(CPURISCVState *env, int csrno, > > static RISCVException write_mstateen0(CPURISCVState *env, int > > csrno, > > target_ulong new_val) > > { > > - uint64_t wr_mask = SMSTATEEN_STATEEN; > > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > > > return write_mstateen(env, csrno, wr_mask, new_val); > > } > > @@ -1843,7 +1912,7 @@ static RISCVException > > write_mstateenh(CPURISCVState *env, int csrno, > > static RISCVException write_mstateen0h(CPURISCVState *env, int > > csrno, > > target_ulong new_val) > > { > > - uint64_t wr_mask = SMSTATEEN_STATEEN; > > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > > > return write_mstateenh(env, csrno, wr_mask, new_val); > > } > > @@ -1892,7 +1961,7 @@ static RISCVException > > write_hstateen(CPURISCVState *env, int csrno, > > static RISCVException write_hstateen0(CPURISCVState *env, int > > csrno, > > target_ulong new_val) > > { > > - uint64_t wr_mask = SMSTATEEN_STATEEN; > > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > > > return write_hstateen(env, csrno, wr_mask, new_val); > > } > > @@ -1943,7 +2012,7 @@ static RISCVException > > write_hstateenh(CPURISCVState *env, int csrno, > > static RISCVException write_hstateen0h(CPURISCVState *env, int > > csrno, > > target_ulong new_val) > > { > > - uint64_t wr_mask = SMSTATEEN_STATEEN; > > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > > > return write_hstateenh(env, csrno, wr_mask, new_val); > > } > > @@ -2002,7 +2071,7 @@ static RISCVException > > write_sstateen(CPURISCVState *env, int csrno, > > static RISCVException write_sstateen0(CPURISCVState *env, int > > csrno, > > target_ulong new_val) > > { > > - uint64_t wr_mask = SMSTATEEN_STATEEN; > > + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > > > return write_sstateen(env, csrno, wr_mask, new_val); > > }
diff --git a/roms/opensbi b/roms/opensbi index 4489876e93..48f91ee9c9 160000 --- a/roms/opensbi +++ b/roms/opensbi @@ -1 +1 @@ -Subproject commit 4489876e933d8ba0d8bc6c64bae71e295d45faac +Subproject commit 48f91ee9c960f048c4a7d1da4447d31e04931e38 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ad1642fb9b..011d6c5976 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -40,6 +40,38 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) } /* Predicates */ +#if !defined(CONFIG_USER_ONLY) +static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, + uint64_t bit) +{ + bool virt = riscv_cpu_virt_enabled(env); + CPUState *cs = env_cpu(env); + RISCVCPU *cpu = RISCV_CPU(cs); + + if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) { + return RISCV_EXCP_NONE; + } + + if (!(env->mstateen[index] & bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (virt) { + if (!(env->hstateen[index] & bit)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + + if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { + if (!(env->sstateen[index] & bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + } + + return RISCV_EXCP_NONE; +} +#endif + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1715,6 +1747,13 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, static RISCVException read_senvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + *val = env->senvcfg; return RISCV_EXCP_NONE; } @@ -1723,15 +1762,27 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, target_ulong val) { uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; + RISCVException ret; - env->senvcfg = (env->senvcfg & ~mask) | (val & mask); + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + env->senvcfg = (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } static RISCVException read_henvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + *val = env->henvcfg; return RISCV_EXCP_NONE; } @@ -1740,6 +1791,12 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, target_ulong val) { uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + RISCVException ret; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } if (riscv_cpu_mxl(env) == MXL_RV64) { mask |= HENVCFG_PBMTE | HENVCFG_STCE; @@ -1753,6 +1810,13 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + *val = env->henvcfg >> 32; return RISCV_EXCP_NONE; } @@ -1762,9 +1826,14 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, { uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; uint64_t valh = (uint64_t)val << 32; + RISCVException ret; - env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); return RISCV_EXCP_NONE; } @@ -1796,7 +1865,7 @@ static RISCVException write_mstateen(CPURISCVState *env, int csrno, static RISCVException write_mstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_mstateen(env, csrno, wr_mask, new_val); } @@ -1843,7 +1912,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno, static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_mstateenh(env, csrno, wr_mask, new_val); } @@ -1892,7 +1961,7 @@ static RISCVException write_hstateen(CPURISCVState *env, int csrno, static RISCVException write_hstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_hstateen(env, csrno, wr_mask, new_val); } @@ -1943,7 +2012,7 @@ static RISCVException write_hstateenh(CPURISCVState *env, int csrno, static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_hstateenh(env, csrno, wr_mask, new_val); } @@ -2002,7 +2071,7 @@ static RISCVException write_sstateen(CPURISCVState *env, int csrno, static RISCVException write_sstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_sstateen(env, csrno, wr_mask, new_val); }
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> --- roms/opensbi | 2 +- target/riscv/csr.c | 83 ++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 77 insertions(+), 8 deletions(-)