| Message ID | 20220708085736.94546-2-kito.cheng@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] util/log: Add vu to dump content of vector unit | expand |
在 2022/7/8 下午4:57, Kito Cheng 写道: > Implement -d cpu,vu to dump content of vector register. > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > --- > target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c1b96da7da..97b289d277 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -72,6 +72,15 @@ const char * const riscv_fpr_regnames[] = { > "f30/ft10", "f31/ft11" > }; > > +const char * const riscv_vr_regnames[] = { > + "v0", "v1", "v2", "v3", "v4", "v5", > + "v6", "v7", "v8", "v9", "v10", "v11", > + "v12", "v13", "v14", "v15", "v16", "v17", > + "v18", "v19", "v20", "v21", "v22", "v23", > + "v24", "v25", "v26", "v27", "v28", "v29", > + "v30", "v31" > +}; > + > static const char * const riscv_excp_names[] = { > "misaligned_fetch", > "fault_fetch", > @@ -375,6 +384,28 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > } > } > } > + if (flags & CPU_DUMP_VU) { > + int vlen = cpu->cfg.vlen; > + int n_chunk = vlen / 64; > + if (vlen == 32) { > + for (i = 0; i < 32; i++) { > + qemu_fprintf(f, "0x%08" PRIx64 "\n", env->vreg[i]); > + } Seems forget to dump the riscv_vr_regnames here. Just another question: whether is it necessary to dump the vector related csrs too? Regards, Weiwei Li > + } else { > + for (i = 0; i < 32; i++) { > + qemu_fprintf(f, " %-8s ", > + riscv_vr_regnames[i]); > + > + int vec_reg_offset = i * vlen / 64; > + qemu_fprintf(f, "0x"); > + for (int j = n_chunk - 1; j >= 0; --j) { > + qemu_fprintf(f, "%016" PRIx64, > + env->vreg[vec_reg_offset + j]); > + } > + qemu_fprintf(f, "\n"); > + } > + } > + } > } > > static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c1b96da7da..97b289d277 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -72,6 +72,15 @@ const char * const riscv_fpr_regnames[] = { "f30/ft10", "f31/ft11" }; +const char * const riscv_vr_regnames[] = { + "v0", "v1", "v2", "v3", "v4", "v5", + "v6", "v7", "v8", "v9", "v10", "v11", + "v12", "v13", "v14", "v15", "v16", "v17", + "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", + "v30", "v31" +}; + static const char * const riscv_excp_names[] = { "misaligned_fetch", "fault_fetch", @@ -375,6 +384,28 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } } + if (flags & CPU_DUMP_VU) { + int vlen = cpu->cfg.vlen; + int n_chunk = vlen / 64; + if (vlen == 32) { + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "0x%08" PRIx64 "\n", env->vreg[i]); + } + } else { + for (i = 0; i < 32; i++) { + qemu_fprintf(f, " %-8s ", + riscv_vr_regnames[i]); + + int vec_reg_offset = i * vlen / 64; + qemu_fprintf(f, "0x"); + for (int j = n_chunk - 1; j >= 0; --j) { + qemu_fprintf(f, "%016" PRIx64, + env->vreg[vec_reg_offset + j]); + } + qemu_fprintf(f, "\n"); + } + } + } } static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
Implement -d cpu,vu to dump content of vector register. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> --- target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)