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[1/2] powerpc/irq: Don't open code irq_soft_mask helpers

Message ID e2454434992cc932a5a34b695ae981c0b2f4c28e.1652862729.git.christophe.leroy@csgroup.eu (mailing list archive)
State Accepted
Headers show
Series [1/2] powerpc/irq: Don't open code irq_soft_mask helpers | expand

Commit Message

Christophe Leroy May 18, 2022, 8:32 a.m. UTC 
Use READ_ONCE() and WRITE_ONCE() instead of open coding
read and write of local PACA irq_soft_mask.

For the write, add a barrier to keep the memory clobber
that was there previously.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
 arch/powerpc/include/asm/hw_irq.h | 43 +++++--------------------------
 1 file changed, 7 insertions(+), 36 deletions(-)

Comments

Michael Ellerman July 4, 2022, 11:33 a.m. UTC | #1 
On Wed, 18 May 2022 10:32:27 +0200, Christophe Leroy wrote:
> Use READ_ONCE() and WRITE_ONCE() instead of open coding
> read and write of local PACA irq_soft_mask.
> 
> For the write, add a barrier to keep the memory clobber
> that was there previously.
> 
> 
> [...]

Applied to powerpc/next.

[1/2] powerpc/irq: Don't open code irq_soft_mask helpers
      https://git.kernel.org/powerpc/c/ef5b570d3700fbb8628a58da0487486ceeb713cd
[2/2] powerpc/irq: Replace #ifdefs by IS_ENABLED()
      https://git.kernel.org/powerpc/c/78ffe6a7e2a169c4dcbbd08717a0a8d738659d15

cheers
diff mbox series

Patch

diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 674e5aaafcbd..edc569481faf 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -113,14 +113,7 @@  static inline void __hard_RI_enable(void)
 
 static inline notrace unsigned long irq_soft_mask_return(void)
 {
-	unsigned long flags;
-
-	asm volatile(
-		"lbz %0,%1(13)"
-		: "=r" (flags)
-		: "i" (offsetof(struct paca_struct, irq_soft_mask)));
-
-	return flags;
+	return READ_ONCE(local_paca->irq_soft_mask);
 }
 
 /*
@@ -148,46 +141,24 @@  static inline notrace void irq_soft_mask_set(unsigned long mask)
 	WARN_ON(mask && !(mask & IRQS_DISABLED));
 #endif
 
-	asm volatile(
-		"stb %0,%1(13)"
-		:
-		: "r" (mask),
-		  "i" (offsetof(struct paca_struct, irq_soft_mask))
-		: "memory");
+	WRITE_ONCE(local_paca->irq_soft_mask, mask);
+	barrier();
 }
 
 static inline notrace unsigned long irq_soft_mask_set_return(unsigned long mask)
 {
-	unsigned long flags;
-
-#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
-	WARN_ON(mask && !(mask & IRQS_DISABLED));
-#endif
+	unsigned long flags = irq_soft_mask_return();
 
-	asm volatile(
-		"lbz %0,%1(13); stb %2,%1(13)"
-		: "=&r" (flags)
-		: "i" (offsetof(struct paca_struct, irq_soft_mask)),
-		  "r" (mask)
-		: "memory");
+	irq_soft_mask_set(mask);
 
 	return flags;
 }
 
 static inline notrace unsigned long irq_soft_mask_or_return(unsigned long mask)
 {
-	unsigned long flags, tmp;
-
-	asm volatile(
-		"lbz %0,%2(13); or %1,%0,%3; stb %1,%2(13)"
-		: "=&r" (flags), "=r" (tmp)
-		: "i" (offsetof(struct paca_struct, irq_soft_mask)),
-		  "r" (mask)
-		: "memory");
+	unsigned long flags = irq_soft_mask_return();
 
-#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
-	WARN_ON((mask | flags) && !((mask | flags) & IRQS_DISABLED));
-#endif
+	irq_soft_mask_set(flags | mask);
 
 	return flags;
 }