Message ID | 20211125073951.57678-5-zhiwei_liu@c-sky.com |
---|---|
State | New |
Headers | show |
Series | Support UXL filed in xstatus | expand |
On 11/25/21 8:39 AM, LIU Zhiwei wrote: > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 3 +++ > target/riscv/cpu_helper.c | 3 ++- > target/riscv/csr.c | 2 ++ > target/riscv/machine.c | 5 +++-- > 5 files changed, 11 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f812998123..5c757ce33a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -377,6 +377,7 @@ static void riscv_cpu_reset(DeviceState *dev) > /* mmte is supposed to have pm.current hardwired to 1 */ > env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); > #endif > + env->xl = riscv_cpu_mxl(env); > cs->exception_index = RISCV_EXCP_NONE; > env->load_res = -1; > set_default_nan_mode(1, &env->fp_status); > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 0760c0af93..412339dbad 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -138,6 +138,7 @@ struct CPURISCVState { > uint32_t misa_mxl_max; /* max mxl for this cpu */ > uint32_t misa_ext; /* current extensions */ > uint32_t misa_ext_mask; /* max ext for this cpu */ > + uint32_t xl; /* current xlen */ > > uint32_t features; > > @@ -420,6 +421,8 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) > } > #endif > > +RISCVMXL cpu_get_xl(CPURISCVState *env); Probably this name should be a define/inline function, just like riscv_cpu_mxl. The proper function should probably be renamed cpu_recompute_xl, or something. > const VMStateDescription vmstate_riscv_cpu = { > .name = "cpu", > - .version_id = 3, > - .minimum_version_id = 3, > + .version_id = 4, > + .minimum_version_id = 4, > .fields = (VMStateField[]) { > VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), > VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), > @@ -183,6 +183,7 @@ const VMStateDescription vmstate_riscv_cpu = { > VMSTATE_UINT32(env.misa_ext, RISCVCPU), > VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), > VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), > + VMSTATE_UINT32(env.xl, RISCVCPU), Do not save this. We prefer to only save architectural state (which is of course required), and recompute anything else (which is qemu internal) from that in the post_load hook. This allows qemu internals to change without breaking compatibility. r~
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..5c757ce33a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -377,6 +377,7 @@ static void riscv_cpu_reset(DeviceState *dev) /* mmte is supposed to have pm.current hardwired to 1 */ env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); #endif + env->xl = riscv_cpu_mxl(env); cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..412339dbad 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -138,6 +138,7 @@ struct CPURISCVState { uint32_t misa_mxl_max; /* max mxl for this cpu */ uint32_t misa_ext; /* current extensions */ uint32_t misa_ext_mask; /* max ext for this cpu */ + uint32_t xl; /* current xlen */ uint32_t features; @@ -420,6 +421,8 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) } #endif +RISCVMXL cpu_get_xl(CPURISCVState *env); + /* * A simplification for VLMAX * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9eeed38c7e..b6cddf8648 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,7 +35,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } -static RISCVMXL cpu_get_xl(CPURISCVState *env) +RISCVMXL cpu_get_xl(CPURISCVState *env) { #if defined(TARGET_RISCV32) return MXL_RV32; @@ -330,6 +330,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) } /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv = newpriv; + env->xl = cpu_get_xl(env); /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ce20c3a970..d4ee897be2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -553,6 +553,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); } env->mstatus = mstatus; + env->xl = cpu_get_xl(env); return RISCV_EXCP_NONE; } @@ -654,6 +655,7 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, /* flush translation cache */ tb_flush(env_cpu(env)); env->misa_ext = val; + env->xl = riscv_cpu_mxl(env); return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ad8248ebfd..08ed603626 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -166,8 +166,8 @@ static const VMStateDescription vmstate_pointermasking = { const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .version_id = 3, - .minimum_version_id = 3, + .version_id = 4, + .minimum_version_id = 4, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -183,6 +183,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT32(env.misa_ext, RISCVCPU), VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), + VMSTATE_UINT32(env.xl, RISCVCPU), VMSTATE_UINT32(env.features, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.virt, RISCVCPU),
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 3 +++ target/riscv/cpu_helper.c | 3 ++- target/riscv/csr.c | 2 ++ target/riscv/machine.c | 5 +++-- 5 files changed, 11 insertions(+), 3 deletions(-)