diff mbox series

[v3,15/20] target/riscv: Remove VILL field in VTYPE

Message ID 20211111055800.42672-16-zhiwei_liu@c-sky.com
State New
Headers show
Series Support UXL filed in xstatus | expand

Commit Message

LIU Zhiwei Nov. 11, 2021, 5:57 a.m. UTC 
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/cpu.h | 1 -
 1 file changed, 1 deletion(-)

Comments

Richard Henderson Nov. 11, 2021, 11:38 a.m. UTC | #1 
On 11/11/21 6:57 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
>   target/riscv/cpu.h | 1 -
>   1 file changed, 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index b48c7c346c..5f35217f7d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2)
>   FIELD(VTYPE, VSEW, 2, 3)
>   FIELD(VTYPE, VEDIV, 5, 2)
>   FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
> -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)

Hmm.  It's sorta-kinda documentation. Otherwise we might as well remove RESERVED as well, 
and just move the 7 constant into vsetvl.

Either way,
Acked-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b48c7c346c..5f35217f7d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -106,7 +106,6 @@  FIELD(VTYPE, VLMUL, 0, 2)
 FIELD(VTYPE, VSEW, 2, 3)
 FIELD(VTYPE, VEDIV, 5, 2)
 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
 
 struct CPURISCVState {
     target_ulong gpr[32];