| Message ID | 20211015192931.227387-6-space.monkey.delivers@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V Pointer Masking implementatio | expand |
On 10/15/21 12:29 PM, Alexey Baturo wrote: > Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/insn_trans/trans_rva.c.inc | 3 +++ > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > target/riscv/translate.c | 10 ++++++++++ > 5 files changed, 19 insertions(+) > > diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc > index 6ea07d89b0..5bdc412191 100644 > --- a/target/riscv/insn_trans/trans_rva.c.inc > +++ b/target/riscv/insn_trans/trans_rva.c.inc > @@ -25,6 +25,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) > if (a->rl) { > tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); > } > + gen_pm_adjust_address(ctx, &src1, src1); ... > +/* > + * Temp stub: generates address adjustment for PointerMasking > + */ > +static void gen_pm_adjust_address(DisasContext *s, > + TCGv *dst, > + TCGv src) > +{ > + tcg_gen_mov_tl(*dst, src); > +} I mentioned before that you would not be able to do this. You are writing to the live cpu register, even if in this case it's a nop. You could, for example, make the stub be *dst = src; but that begs the question of why not use the return value, and have the stub be return src; r~
Hi, Sorry, my bad, got it wrong. Fixed now. Thanks! сб, 16 окт. 2021 г. в 02:49, Richard Henderson <richard.henderson@linaro.org >: > On 10/15/21 12:29 PM, Alexey Baturo wrote: > > Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > target/riscv/insn_trans/trans_rva.c.inc | 3 +++ > > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > > target/riscv/translate.c | 10 ++++++++++ > > 5 files changed, 19 insertions(+) > > > > diff --git a/target/riscv/insn_trans/trans_rva.c.inc > b/target/riscv/insn_trans/trans_rva.c.inc > > index 6ea07d89b0..5bdc412191 100644 > > --- a/target/riscv/insn_trans/trans_rva.c.inc > > +++ b/target/riscv/insn_trans/trans_rva.c.inc > > @@ -25,6 +25,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, > MemOp mop) > > if (a->rl) { > > tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); > > } > > + gen_pm_adjust_address(ctx, &src1, src1); > ... > > +/* > > + * Temp stub: generates address adjustment for PointerMasking > > + */ > > +static void gen_pm_adjust_address(DisasContext *s, > > + TCGv *dst, > > + TCGv src) > > +{ > > + tcg_gen_mov_tl(*dst, src); > > +} > > I mentioned before that you would not be able to do this. > You are writing to the live cpu register, even if in this case it's a nop. > > You could, for example, make the stub be > > *dst = src; > > but that begs the question of why not use the return value, and have the > stub be > > return src; > > > r~ >
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index 6ea07d89b0..5bdc412191 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -25,6 +25,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } + gen_pm_adjust_address(ctx, &src1, src1); tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -44,6 +45,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) TCGLabel *l2 = gen_new_label(); src1 = get_gpr(ctx, a->rs1, EXT_ZERO); + gen_pm_adjust_address(ctx, &src1, src1); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); /* @@ -84,6 +86,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + gen_pm_adjust_address(ctx, &src1, src1); func(dest, src1, src2, ctx->mem_idx, mop); gen_set_gpr(ctx, a->rd, dest); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index db9ae15755..40e73d9959 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -31,6 +31,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } + gen_pm_adjust_address(ctx, &addr, addr); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ); @@ -51,6 +52,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } + gen_pm_adjust_address(ctx, &addr, addr); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index bddbd418d9..945dc75fdc 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -37,6 +37,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } + gen_pm_adjust_address(ctx, &addr, addr); dest = cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); @@ -59,6 +60,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } + gen_pm_adjust_address(ctx, &addr, addr); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 920ae0edb3..d4097b59f7 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -146,6 +146,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } + gen_pm_adjust_address(ctx, &addr, addr); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, dest); @@ -187,6 +188,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } + gen_pm_adjust_address(ctx, &addr, addr); tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); return true; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d2442f0cf5..95739b1e41 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -118,6 +118,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); } +/* + * Temp stub: generates address adjustment for PointerMasking + */ +static void gen_pm_adjust_address(DisasContext *s, + TCGv *dst, + TCGv src) +{ + tcg_gen_mov_tl(*dst, src); +} + /* * A narrow n-bit operation, where n < FLEN, checks that input operands * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.