Message ID | 20210903170100.2529121-4-philipp.tomsich@vrull.eu |
---|---|
State | New |
Headers | show |
Series | target/riscv: Update QEmu for Zb[abcs] 1.0.0 | expand |
On 9/3/21 7:00 PM, Philipp Tomsich wrote: > @@ -652,5 +652,15 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_ZBA(ctx); > + > + /* > + * The shamt field is only 6 bits for RV64 (with the 7th bit > + * remaining reserved for RV128). If the reserved bit is set > + * on RV64, the encoding is illegal. > + */ > + if (a->shamt >= TARGET_LONG_BITS) { > + return false; > + } > + > return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); As previously stated, drop this patch. It is done correctly inside gen_shift_imm_fn. r~
On Fri, 3 Sept 2021 at 21:45, Richard Henderson < richard.henderson@linaro.org> wrote: > On 9/3/21 7:00 PM, Philipp Tomsich wrote: > > @@ -652,5 +652,15 @@ static bool trans_slli_uw(DisasContext *ctx, > arg_slli_uw *a) > > { > > REQUIRE_64BIT(ctx); > > REQUIRE_ZBA(ctx); > > + > > + /* > > + * The shamt field is only 6 bits for RV64 (with the 7th bit > > + * remaining reserved for RV128). If the reserved bit is set > > + * on RV64, the encoding is illegal. > > + */ > > + if (a->shamt >= TARGET_LONG_BITS) { > > + return false; > > + } > > + > > return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); > > As previously stated, drop this patch. > It is done correctly inside gen_shift_imm_fn. Good catch: I just looked through the changed translate.c and this does address the slli.uw case. I won't be able to retest this tonight, though. I'll send the updated series as soon as possible, though.
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 91da7c5853..77114889de 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -652,5 +652,15 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBA(ctx); + + /* + * The shamt field is only 6 bits for RV64 (with the 7th bit + * remaining reserved for RV128). If the reserved bit is set + * on RV64, the encoding is illegal. + */ + if (a->shamt >= TARGET_LONG_BITS) { + return false; + } + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); }