Message ID | 1314254480-22438-13-git-send-email-peter.crosthwaite@petalogix.com |
---|---|
State | New |
Headers | show |
On 25 August 2011 07:41, Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> wrote: > From: Edgar E. Iglesias <edgar.iglesias@petalogix.com> > > Instead of hardcoding it to 1. This and patch 13/14 seem to be generic target-microblaze fixes -- did you mean to include them in this devicetree series rather than sending them separately? -- PMM
Hi Peter , I included them as they are prerequisite for patch 14. Edgar, can we get a review / push of these two separate of this series so I can take them out next revision ? On Aug 25, 2011 7:34 PM, "Peter Maydell" <peter.maydell@linaro.org> wrote: On 25 August 2011 07:41, Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> wrote: > From: Edgar E. Iglesias <edgar.iglesias@petalogix.com> > ... This and patch 13/14 seem to be generic target-microblaze fixes -- did you mean to include them in this devicetree series rather than sending them separately? -- PMM
On Thu, Aug 25, 2011 at 08:17:35PM +1000, Peter Crosthwaite wrote: > Hi Peter , I included them as they are prerequisite for patch 14. Edgar, can we > get a review / push of these two separate of this series so I can take them out > next revision ? Yes, my bad. I should have pushed this before. Thanks
On Thu, Aug 25, 2011 at 08:17:35PM +1000, Peter Crosthwaite wrote: > Hi Peter , I included them as they are prerequisite for patch 14. Edgar, can we > get a review / push of these two separate of this series so I can take them out > next revision ? I've applied this now, thanks. Cheers
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 1a862d3..15f1fe5 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -424,10 +424,15 @@ static inline void msr_read(DisasContext *dc, TCGv d) static inline void msr_write(DisasContext *dc, TCGv v) { + TCGv t; + + t = tcg_temp_new(); dc->cpustate_changed = 1; - tcg_gen_mov_tl(cpu_SR[SR_MSR], v); - /* PVR, we have a processor version register. */ - tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10)); + /* PVR bit is not writable. */ + tcg_gen_andi_tl(t, v, ~(1 << 10)); + tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10)); + tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v); + tcg_temp_free(t); } static void dec_msr(DisasContext *dc)