Message ID | 20201216020150.3157-16-frank.chang@sifive.com |
---|---|
State | New |
Headers | show |
Series | support subsets of bitmanip extension | expand |
Hi Alistair, Frank:
Should we add the bext_spec option like Vector-ext? I would suggest
adding one to align the behavior between V and B.
But I have no strong opinion for this.
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
On 12/16/20 3:14 AM, Kito Cheng wrote: > Hi Alistair, Frank: > > Should we add the bext_spec option like Vector-ext? I would suggest > adding one to align the behavior between V and B. > But I have no strong opinion for this. > I don't think there's any point in that. The experimental extension will be updated without backward compatibility until it reaches 1.0. After which we could add one, *if* we expected there to be future incompatible changes. r~
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a0264fc6b1..33fa112c4ac 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -441,6 +441,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_h) { target_misa |= RVH; } + if (cpu->cfg.ext_b) { + target_misa |= RVB; + } if (cpu->cfg.ext_v) { target_misa |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { @@ -511,6 +514,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c8430..4868f62f32b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVB RV('B') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -276,6 +277,7 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; + bool ext_b; bool ext_s; bool ext_u; bool ext_h;