| Message ID | 1600257900-2043-1-git-send-email-atrajeev@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (27e2fbcd815a088d7d83c7158f76b6e95ab07c50) |
| snowpatch_ozlabs/build-ppc64le | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-ppc64be | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-ppc64e | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-pmac32 | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 16 lines checked |
| snowpatch_ozlabs/needsstable | warning | Please consider tagging this patch for stable! |
Athira Rajeev <atrajeev@linux.vnet.ibm.com> writes: > PMU counter support functions enforces event constraints for group of > events to check if all events in a group can be monitored. Incase of > event codes using PMC5 and PMC6 ( 500fa and 600f4 respectively ), > not all constraints are applicable, say the threshold or sample bits. > But current code includes pmc5 and pmc6 in some group constraints (like > IC_DC Qualifier bits) which is actually not applicable and hence results > in those events not getting counted when scheduled along with group of > other events. Patch fixes this by excluding PMC5/6 from constraints > which are not relevant for it. > > Fixes: 7ffd948 ('powerpc/perf: factor out power8 pmu functions') > Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> > --- > arch/powerpc/perf/isa207-common.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c > index 964437a..186fad8 100644 > --- a/arch/powerpc/perf/isa207-common.c > +++ b/arch/powerpc/perf/isa207-common.c > @@ -288,6 +288,9 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) > > mask |= CNST_PMC_MASK(pmc); > value |= CNST_PMC_VAL(pmc); > + > + if (pmc >= 5) > + goto ebb_bhrb; This is fairly subtle. Can you please put a block comment above the if explaining in a few lines what's going on. cheers
> On 17-Sep-2020, at 5:43 PM, Michael Ellerman <mpe@ellerman.id.au> wrote: > > Athira Rajeev <atrajeev@linux.vnet.ibm.com> writes: >> PMU counter support functions enforces event constraints for group of >> events to check if all events in a group can be monitored. Incase of >> event codes using PMC5 and PMC6 ( 500fa and 600f4 respectively ), >> not all constraints are applicable, say the threshold or sample bits. >> But current code includes pmc5 and pmc6 in some group constraints (like >> IC_DC Qualifier bits) which is actually not applicable and hence results >> in those events not getting counted when scheduled along with group of >> other events. Patch fixes this by excluding PMC5/6 from constraints >> which are not relevant for it. >> >> Fixes: 7ffd948 ('powerpc/perf: factor out power8 pmu functions') >> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> >> --- >> arch/powerpc/perf/isa207-common.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c >> index 964437a..186fad8 100644 >> --- a/arch/powerpc/perf/isa207-common.c >> +++ b/arch/powerpc/perf/isa207-common.c >> @@ -288,6 +288,9 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) >> >> mask |= CNST_PMC_MASK(pmc); >> value |= CNST_PMC_VAL(pmc); >> + >> + if (pmc >= 5) >> + goto ebb_bhrb; > > This is fairly subtle. Can you please put a block comment above the if > explaining in a few lines what's going on. Hi Michael, Sure, I will include a comment explaining the change in V2. Thanks Athira > > cheers
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c index 964437a..186fad8 100644 --- a/arch/powerpc/perf/isa207-common.c +++ b/arch/powerpc/perf/isa207-common.c @@ -288,6 +288,9 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) mask |= CNST_PMC_MASK(pmc); value |= CNST_PMC_VAL(pmc); + + if (pmc >= 5) + goto ebb_bhrb; } if (pmc <= 4) { @@ -357,6 +360,7 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) } } +ebb_bhrb: if (!pmc && ebb) /* EBB events must specify the PMC */ return -1;
PMU counter support functions enforces event constraints for group of events to check if all events in a group can be monitored. Incase of event codes using PMC5 and PMC6 ( 500fa and 600f4 respectively ), not all constraints are applicable, say the threshold or sample bits. But current code includes pmc5 and pmc6 in some group constraints (like IC_DC Qualifier bits) which is actually not applicable and hence results in those events not getting counted when scheduled along with group of other events. Patch fixes this by excluding PMC5/6 from constraints which are not relevant for it. Fixes: 7ffd948 ('powerpc/perf: factor out power8 pmu functions') Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> --- arch/powerpc/perf/isa207-common.c | 4 ++++ 1 file changed, 4 insertions(+)