| Message ID | 20200703063626.1412544-1-anju@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | powerpc/perf: Add kernel support for new MSR[HV PR] bits in trace-imc. | expand |
On 7/3/20 12:06 PM, Anju T Sudhakar wrote: > IMC trace-mode record has MSR[HV PR] bits added in the third DW. > These bits can be used to set the cpumode for the instruction pointer > captured in each sample. > > Add support in kernel to use these bits to set the cpumode for > each sample. > Changes looks fine to me. Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com> > > Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> > --- > arch/powerpc/include/asm/imc-pmu.h | 5 +++++ > arch/powerpc/perf/imc-pmu.c | 29 ++++++++++++++++++++++++----- > 2 files changed, 29 insertions(+), 5 deletions(-) > > diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h > index 4da4fcba0684..4f897993b710 100644 > --- a/arch/powerpc/include/asm/imc-pmu.h > +++ b/arch/powerpc/include/asm/imc-pmu.h > @@ -99,6 +99,11 @@ struct trace_imc_data { > */ > #define IMC_TRACE_RECORD_TB1_MASK 0x3ffffffffffULL > > +/* > + * Bit 0:1 in third DW of IMC trace record > + * specifies the MSR[HV PR] values. > + */ > +#define IMC_TRACE_RECORD_VAL_HVPR(x) ((x) >> 62) > > /* > * Device tree parser code detects IMC pmu support and > diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c > index cb50a9e1fd2d..310922fed9eb 100644 > --- a/arch/powerpc/perf/imc-pmu.c > +++ b/arch/powerpc/perf/imc-pmu.c > @@ -1178,11 +1178,30 @@ static int trace_imc_prepare_sample(struct trace_imc_data *mem, > header->size = sizeof(*header) + event->header_size; > header->misc = 0; > > - if (is_kernel_addr(data->ip)) > - header->misc |= PERF_RECORD_MISC_KERNEL; > - else > - header->misc |= PERF_RECORD_MISC_USER; > - > + if (cpu_has_feature(CPU_FTRS_POWER9)) { > + if (is_kernel_addr(data->ip)) > + header->misc |= PERF_RECORD_MISC_KERNEL; > + else > + header->misc |= PERF_RECORD_MISC_USER; > + } else { > + switch (IMC_TRACE_RECORD_VAL_HVPR(mem->val)) { > + case 0:/* when MSR HV and PR not set in the trace-record */ > + header->misc |= PERF_RECORD_MISC_GUEST_KERNEL; > + break; > + case 1: /* MSR HV is 0 and PR is 1 */ > + header->misc |= PERF_RECORD_MISC_GUEST_USER; > + break; > + case 2: /* MSR Hv is 1 and PR is 0 */ > + header->misc |= PERF_RECORD_MISC_HYPERVISOR; > + break; > + case 3: /* MSR HV is 1 and PR is 1 */ > + header->misc |= PERF_RECORD_MISC_USER; > + break; > + default: > + pr_info("IMC: Unable to set the flag based on MSR bits\n"); > + break; > + } > + } > perf_event_header__init_id(header, data, event); > > return 0;
diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h index 4da4fcba0684..4f897993b710 100644 --- a/arch/powerpc/include/asm/imc-pmu.h +++ b/arch/powerpc/include/asm/imc-pmu.h @@ -99,6 +99,11 @@ struct trace_imc_data { */ #define IMC_TRACE_RECORD_TB1_MASK 0x3ffffffffffULL +/* + * Bit 0:1 in third DW of IMC trace record + * specifies the MSR[HV PR] values. + */ +#define IMC_TRACE_RECORD_VAL_HVPR(x) ((x) >> 62) /* * Device tree parser code detects IMC pmu support and diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index cb50a9e1fd2d..310922fed9eb 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -1178,11 +1178,30 @@ static int trace_imc_prepare_sample(struct trace_imc_data *mem, header->size = sizeof(*header) + event->header_size; header->misc = 0; - if (is_kernel_addr(data->ip)) - header->misc |= PERF_RECORD_MISC_KERNEL; - else - header->misc |= PERF_RECORD_MISC_USER; - + if (cpu_has_feature(CPU_FTRS_POWER9)) { + if (is_kernel_addr(data->ip)) + header->misc |= PERF_RECORD_MISC_KERNEL; + else + header->misc |= PERF_RECORD_MISC_USER; + } else { + switch (IMC_TRACE_RECORD_VAL_HVPR(mem->val)) { + case 0:/* when MSR HV and PR not set in the trace-record */ + header->misc |= PERF_RECORD_MISC_GUEST_KERNEL; + break; + case 1: /* MSR HV is 0 and PR is 1 */ + header->misc |= PERF_RECORD_MISC_GUEST_USER; + break; + case 2: /* MSR Hv is 1 and PR is 0 */ + header->misc |= PERF_RECORD_MISC_HYPERVISOR; + break; + case 3: /* MSR HV is 1 and PR is 1 */ + header->misc |= PERF_RECORD_MISC_USER; + break; + default: + pr_info("IMC: Unable to set the flag based on MSR bits\n"); + break; + } + } perf_event_header__init_id(header, data, event); return 0;
IMC trace-mode record has MSR[HV PR] bits added in the third DW. These bits can be used to set the cpumode for the instruction pointer captured in each sample. Add support in kernel to use these bits to set the cpumode for each sample. Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> --- arch/powerpc/include/asm/imc-pmu.h | 5 +++++ arch/powerpc/perf/imc-pmu.c | 29 ++++++++++++++++++++++++----- 2 files changed, 29 insertions(+), 5 deletions(-)