| Message ID | 20200309085806.155823-1-ravi.bangoria@linux.ibm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | powerpc/watchpoint: Preparation for more than one watchpoint | expand |
Le 09/03/2020 à 09:57, Ravi Bangoria a écrit : > So far, powerpc Book3S code has been written with an assumption of only > one watchpoint. But future power architecture is introducing second > watchpoint register (DAWR). Even though this patchset does not enable > 2nd DAWR, it make the infrastructure ready so that enabling 2nd DAWR > should just be a matter of changing count. Some book3s (e300 family for instance, I think G2 as well) already have a DABR2 in addition to DABR. Will this series allow to use it as well ? Christophe
On Mon, Mar 16, 2020 at 04:05:01PM +0100, Christophe Leroy wrote: > Some book3s (e300 family for instance, I think G2 as well) already have > a DABR2 in addition to DABR. The original "G2" (meaning 603 and 604) do not have DABR2. The newer "G2" (meaning e300) does have it. e500 and e600 do not have it either. Hope I got that right ;-) Segher
Le 16/03/2020 à 19:43, Segher Boessenkool a écrit : > On Mon, Mar 16, 2020 at 04:05:01PM +0100, Christophe Leroy wrote: >> Some book3s (e300 family for instance, I think G2 as well) already have >> a DABR2 in addition to DABR. > > The original "G2" (meaning 603 and 604) do not have DABR2. The newer > "G2" (meaning e300) does have it. e500 and e600 do not have it either. > > Hope I got that right ;-) > > G2 core reference manual says: Features specific to the G2 core not present on the original MPC603e (PID6-603e) processors follow: ... Enhanced debug features — Addition of three breakpoint registers—IABR2, DABR, and DABR2 — Two new breakpoint control registers—DBCR and IBCR e500 has DAC1 and DAC2 instead for breakpoints iaw e500 core reference manual. Christophe
On 3/16/20 8:35 PM, Christophe Leroy wrote: > > > Le 09/03/2020 à 09:57, Ravi Bangoria a écrit : >> So far, powerpc Book3S code has been written with an assumption of only >> one watchpoint. But future power architecture is introducing second >> watchpoint register (DAWR). Even though this patchset does not enable >> 2nd DAWR, it make the infrastructure ready so that enabling 2nd DAWR >> should just be a matter of changing count. > > Some book3s (e300 family for instance, I think G2 as well) already have a DABR2 in addition to DABR. > Will this series allow to use it as well ? I wasn't aware of that. I'll take a look at their specs and check if they can piggyback on this series for 2nd DABR. Thanks, Ravi
On 3/18/20 6:22 PM, Ravi Bangoria wrote: > > > On 3/16/20 8:35 PM, Christophe Leroy wrote: >> >> >> Le 09/03/2020 à 09:57, Ravi Bangoria a écrit : >>> So far, powerpc Book3S code has been written with an assumption of only >>> one watchpoint. But future power architecture is introducing second >>> watchpoint register (DAWR). Even though this patchset does not enable >>> 2nd DAWR, it make the infrastructure ready so that enabling 2nd DAWR >>> should just be a matter of changing count. >> >> Some book3s (e300 family for instance, I think G2 as well) already have a DABR2 in addition to DABR. >> Will this series allow to use it as well ? > > I wasn't aware of that. I'll take a look at their specs and check if they > can piggyback on this series for 2nd DABR. There are some differences between G2/e300 DABRs and Book3S DAWRs. G2/e300 DABRs provides some functionalities like "Match if EA less/greater than DABR", "combined mode" etc. are not present with DAWRs. DBCR on G2/e300 also provides which DABR caused the exception. So this series might not directly allow to use DABR2 but, I guess, it should work as base infrastructure. Ravi
So far, powerpc Book3S code has been written with an assumption of only one watchpoint. But future power architecture is introducing second watchpoint register (DAWR). Even though this patchset does not enable 2nd DAWR, it make the infrastructure ready so that enabling 2nd DAWR should just be a matter of changing count. Existing functionality works fine with the patchset. I've tested it with perf, ptrace(gdb), xmon. All hw-breakpoint selftests are passing as well. And I've build tested for 8xx. Note: kvm or PowerVM geust is not enabled yet. The series applies fine to powerpc/next plus one more dependency patch: https://git.kernel.org/powerpc/c/e08658a657f974590809290c62e889f0fd420200 Ravi Bangoria (15): powerpc/watchpoint: Rename current DAWR macros powerpc/watchpoint: Add SPRN macros for second DAWR powerpc/watchpoint: Introduce function to get nr watchpoints dynamically powerpc/watchpoint/ptrace: Return actual num of available watchpoints powerpc/watchpoint: Provide DAWR number to set_dawr powerpc/watchpoint: Provide DAWR number to __set_breakpoint powerpc/watchpoint: Get watchpoint count dynamically while disabling them powerpc/watchpoint: Disable all available watchpoints when !dawr_force_enable powerpc/watchpoint: Convert thread_struct->hw_brk to an array powerpc/watchpoint: Use loop for thread_struct->ptrace_bps powerpc/watchpoint: Introduce is_ptrace_bp() function powerpc/watchpoint: Prepare handler to handle more than one watcnhpoint powerpc/watchpoint: Don't allow concurrent perf and ptrace events powerpc/watchpoint/xmon: Don't allow breakpoint overwriting powerpc/watchpoint/xmon: Support 2nd dawr arch/powerpc/include/asm/cputable.h | 6 +- arch/powerpc/include/asm/debug.h | 2 +- arch/powerpc/include/asm/hw_breakpoint.h | 23 +- arch/powerpc/include/asm/processor.h | 6 +- arch/powerpc/include/asm/reg.h | 6 +- arch/powerpc/include/asm/sstep.h | 2 + arch/powerpc/kernel/dawr.c | 23 +- arch/powerpc/kernel/hw_breakpoint.c | 628 +++++++++++++++++++---- arch/powerpc/kernel/process.c | 66 ++- arch/powerpc/kernel/ptrace.c | 72 ++- arch/powerpc/kernel/ptrace32.c | 4 +- arch/powerpc/kernel/signal.c | 9 +- arch/powerpc/kvm/book3s_hv.c | 12 +- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 18 +- arch/powerpc/xmon/xmon.c | 99 ++-- kernel/events/hw_breakpoint.c | 16 + 16 files changed, 793 insertions(+), 199 deletions(-)