Message ID | 157541983500.46157.10867081966222391072.stgit@naples-babu.amd.com |
---|---|
State | New |
Headers | show |
Series | APIC ID fixes for AMD EPYC CPU models | expand |
On Tue, 03 Dec 2019 18:37:15 -0600 Babu Moger <babu.moger@amd.com> wrote: > Now that we have all the parameters in X86CPUTopoInfo, we can just pass the > structure to calculate the offsets and width. > > Signed-off-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> > --- > include/hw/i386/topology.h | 64 ++++++++++++++------------------------------ > target/i386/cpu.c | 23 ++++++++-------- > 2 files changed, 32 insertions(+), 55 deletions(-) > > diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h > index cf1935d548..ba52d49079 100644 > --- a/include/hw/i386/topology.h > +++ b/include/hw/i386/topology.h > @@ -69,56 +69,42 @@ static unsigned apicid_bitwidth_for_count(unsigned count) > > /* Bit width of the SMT_ID (thread ID) field on the APIC ID > */ > -static inline unsigned apicid_smt_width(unsigned nr_dies, > - unsigned nr_cores, > - unsigned nr_threads) > +static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) > { > - return apicid_bitwidth_for_count(nr_threads); > + return apicid_bitwidth_for_count(topo_info->threads_per_core); > } > > /* Bit width of the Core_ID field > */ > -static inline unsigned apicid_core_width(unsigned nr_dies, > - unsigned nr_cores, > - unsigned nr_threads) > +static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) > { > - return apicid_bitwidth_for_count(nr_cores); > + return apicid_bitwidth_for_count(topo_info->cores_per_die); > } > > /* Bit width of the Die_ID field */ > -static inline unsigned apicid_die_width(unsigned nr_dies, > - unsigned nr_cores, > - unsigned nr_threads) > +static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info) > { > - return apicid_bitwidth_for_count(nr_dies); > + return apicid_bitwidth_for_count(topo_info->dies_per_pkg); > } > > /* Bit offset of the Core_ID field > */ > -static inline unsigned apicid_core_offset(unsigned nr_dies, > - unsigned nr_cores, > - unsigned nr_threads) > +static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) > { > - return apicid_smt_width(nr_dies, nr_cores, nr_threads); > + return apicid_smt_width(topo_info); > } > > /* Bit offset of the Die_ID field */ > -static inline unsigned apicid_die_offset(unsigned nr_dies, > - unsigned nr_cores, > - unsigned nr_threads) > +static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) > { > - return apicid_core_offset(nr_dies, nr_cores, nr_threads) + > - apicid_core_width(nr_dies, nr_cores, nr_threads); > + return apicid_core_offset(topo_info) + apicid_core_width(topo_info); > } > > /* Bit offset of the Pkg_ID (socket ID) field > */ > -static inline unsigned apicid_pkg_offset(unsigned nr_dies, > - unsigned nr_cores, > - unsigned nr_threads) > +static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) > { > - return apicid_die_offset(nr_dies, nr_cores, nr_threads) + > - apicid_die_width(nr_dies, nr_cores, nr_threads); > + return apicid_die_offset(topo_info) + apicid_die_width(topo_info); > } > > /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID > @@ -128,13 +114,9 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies, > static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, > const X86CPUTopoIDs *topo_ids) > { > - unsigned nr_dies = topo_info->dies_per_pkg; > - unsigned nr_cores = topo_info->cores_per_die; > - unsigned nr_threads = topo_info->threads_per_core; > - > - return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | > - (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | > - (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | > + return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | > + (topo_ids->die_id << apicid_die_offset(topo_info)) | > + (topo_ids->core_id << apicid_core_offset(topo_info)) | > topo_ids->smt_id; > } > > @@ -162,19 +144,15 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, > X86CPUTopoInfo *topo_info, > X86CPUTopoIDs *topo_ids) > { > - unsigned nr_dies = topo_info->dies_per_pkg; > - unsigned nr_cores = topo_info->cores_per_die; > - unsigned nr_threads = topo_info->threads_per_core; > - > topo_ids->smt_id = apicid & > - ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads)); > + ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); > topo_ids->core_id = > - (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & > - ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads)); > + (apicid >> apicid_core_offset(topo_info)) & > + ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); > topo_ids->die_id = > - (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & > - ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads)); > - topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); > + (apicid >> apicid_die_offset(topo_info)) & > + ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); > + topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info); > } > > /* Make APIC ID for the CPU 'cpu_index' > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 07cf562d89..bc9b491557 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -4551,6 +4551,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > uint32_t die_offset; > uint32_t limit; > uint32_t signature[3]; > + X86CPUTopoInfo topo_info; > + > + topo_info.dies_per_pkg = env->nr_dies; > + topo_info.cores_per_die = cs->nr_cores; > + topo_info.threads_per_core = cs->nr_threads; > > /* Calculate & apply limits for different index ranges */ > if (index >= 0xC0000000) { > @@ -4637,8 +4642,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > eax, ebx, ecx, edx); > break; > case 3: /* L3 cache info */ > - die_offset = apicid_die_offset(env->nr_dies, > - cs->nr_cores, cs->nr_threads); > + die_offset = apicid_die_offset(&topo_info); > if (cpu->enable_l3_cache) { > encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, > (1 << die_offset), cs->nr_cores, > @@ -4729,14 +4733,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > > switch (count) { > case 0: > - *eax = apicid_core_offset(env->nr_dies, > - cs->nr_cores, cs->nr_threads); > + *eax = apicid_core_offset(&topo_info); > *ebx = cs->nr_threads; > *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; > break; > case 1: > - *eax = apicid_pkg_offset(env->nr_dies, > - cs->nr_cores, cs->nr_threads); > + *eax = apicid_pkg_offset(&topo_info); > *ebx = cs->nr_cores * cs->nr_threads; > *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; > break; > @@ -4760,20 +4762,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > *edx = cpu->apic_id; > switch (count) { > case 0: > - *eax = apicid_core_offset(env->nr_dies, cs->nr_cores, > - cs->nr_threads); > + *eax = apicid_core_offset(&topo_info); > *ebx = cs->nr_threads; > *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; > break; > case 1: > - *eax = apicid_die_offset(env->nr_dies, cs->nr_cores, > - cs->nr_threads); > + *eax = apicid_die_offset(&topo_info); > *ebx = cs->nr_cores * cs->nr_threads; > *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; > break; > case 2: > - *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores, > - cs->nr_threads); > + *eax = apicid_pkg_offset(&topo_info); > *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; > *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; > break; >
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index cf1935d548..ba52d49079 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -69,56 +69,42 @@ static unsigned apicid_bitwidth_for_count(unsigned count) /* Bit width of the SMT_ID (thread ID) field on the APIC ID */ -static inline unsigned apicid_smt_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(nr_threads); + return apicid_bitwidth_for_count(topo_info->threads_per_core); } /* Bit width of the Core_ID field */ -static inline unsigned apicid_core_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(nr_cores); + return apicid_bitwidth_for_count(topo_info->cores_per_die); } /* Bit width of the Die_ID field */ -static inline unsigned apicid_die_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(nr_dies); + return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } /* Bit offset of the Core_ID field */ -static inline unsigned apicid_core_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) { - return apicid_smt_width(nr_dies, nr_cores, nr_threads); + return apicid_smt_width(topo_info); } /* Bit offset of the Die_ID field */ -static inline unsigned apicid_die_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) { - return apicid_core_offset(nr_dies, nr_cores, nr_threads) + - apicid_core_width(nr_dies, nr_cores, nr_threads); + return apicid_core_offset(topo_info) + apicid_core_width(topo_info); } /* Bit offset of the Pkg_ID (socket ID) field */ -static inline unsigned apicid_pkg_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) { - return apicid_die_offset(nr_dies, nr_cores, nr_threads) + - apicid_die_width(nr_dies, nr_cores, nr_threads); + return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID @@ -128,13 +114,9 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies, static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) { - unsigned nr_dies = topo_info->dies_per_pkg; - unsigned nr_cores = topo_info->cores_per_die; - unsigned nr_threads = topo_info->threads_per_core; - - return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | - (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | - (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | + return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | + (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->core_id << apicid_core_offset(topo_info)) | topo_ids->smt_id; } @@ -162,19 +144,15 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, X86CPUTopoInfo *topo_info, X86CPUTopoIDs *topo_ids) { - unsigned nr_dies = topo_info->dies_per_pkg; - unsigned nr_cores = topo_info->cores_per_die; - unsigned nr_threads = topo_info->threads_per_core; - topo_ids->smt_id = apicid & - ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads)); + ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); topo_ids->core_id = - (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & - ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads)); + (apicid >> apicid_core_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); topo_ids->die_id = - (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & - ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads)); - topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); + (apicid >> apicid_die_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); + topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info); } /* Make APIC ID for the CPU 'cpu_index' diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 07cf562d89..bc9b491557 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4551,6 +4551,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t die_offset; uint32_t limit; uint32_t signature[3]; + X86CPUTopoInfo topo_info; + + topo_info.dies_per_pkg = env->nr_dies; + topo_info.cores_per_die = cs->nr_cores; + topo_info.threads_per_core = cs->nr_threads; /* Calculate & apply limits for different index ranges */ if (index >= 0xC0000000) { @@ -4637,8 +4642,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset = apicid_die_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + die_offset = apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, (1 << die_offset), cs->nr_cores, @@ -4729,14 +4733,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, switch (count) { case 0: - *eax = apicid_core_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + *eax = apicid_core_offset(&topo_info); *ebx = cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax = apicid_pkg_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + *eax = apicid_pkg_offset(&topo_info); *ebx = cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; @@ -4760,20 +4762,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = cpu->apic_id; switch (count) { case 0: - *eax = apicid_core_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax = apicid_core_offset(&topo_info); *ebx = cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax = apicid_die_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax = apicid_die_offset(&topo_info); *ebx = cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: - *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax = apicid_pkg_offset(&topo_info); *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; break;
Now that we have all the parameters in X86CPUTopoInfo, we can just pass the structure to calculate the offsets and width. Signed-off-by: Babu Moger <babu.moger@amd.com> --- include/hw/i386/topology.h | 64 ++++++++++++++------------------------------ target/i386/cpu.c | 23 ++++++++-------- 2 files changed, 32 insertions(+), 55 deletions(-)