| Message ID | 20200108200020.4745-4-nieklinnenbank@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add Allwinner H3 SoC and Orange Pi PC Machine | expand |
Hi, Just a friendly reminder for review of this patch and the others in this series that don't yet have a reviewed-by tag :-) Regards, Niek On Wed, Jan 8, 2020 at 9:00 PM Niek Linnenbank <nieklinnenbank@gmail.com> wrote: > The Clock Control Unit is responsible for clock signal generation, > configuration and distribution in the Allwinner H3 System on Chip. > This commit adds support for the Clock Control Unit which emulates > a simple read/write register interface. > > Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> > --- > include/hw/arm/allwinner-h3.h | 3 + > include/hw/misc/allwinner-h3-ccu.h | 67 ++++++++ > hw/arm/allwinner-h3.c | 9 +- > hw/misc/allwinner-h3-ccu.c | 243 +++++++++++++++++++++++++++++ > hw/misc/Makefile.objs | 1 + > 5 files changed, 322 insertions(+), 1 deletion(-) > create mode 100644 include/hw/misc/allwinner-h3-ccu.h > create mode 100644 hw/misc/allwinner-h3-ccu.c > > diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h > index 4e2e6202a9..0dc18b927a 100644 > --- a/include/hw/arm/allwinner-h3.h > +++ b/include/hw/arm/allwinner-h3.h > @@ -43,6 +43,7 @@ > #include "hw/arm/boot.h" > #include "hw/timer/allwinner-a10-pit.h" > #include "hw/intc/arm_gic.h" > +#include "hw/misc/allwinner-h3-ccu.h" > #include "target/arm/cpu.h" > > /** > @@ -59,6 +60,7 @@ enum { > AW_H3_SRAM_A1, > AW_H3_SRAM_A2, > AW_H3_SRAM_C, > + AW_H3_CCU, > AW_H3_PIT, > AW_H3_UART0, > AW_H3_UART1, > @@ -98,6 +100,7 @@ typedef struct AwH3State { > ARMCPU cpus[AW_H3_NUM_CPUS]; > const hwaddr *memmap; > AwA10PITState timer; > + AwH3ClockCtlState ccu; > GICState gic; > MemoryRegion sram_a1; > MemoryRegion sram_a2; > diff --git a/include/hw/misc/allwinner-h3-ccu.h > b/include/hw/misc/allwinner-h3-ccu.h > new file mode 100644 > index 0000000000..0dcb08ecd1 > --- /dev/null > +++ b/include/hw/misc/allwinner-h3-ccu.h > @@ -0,0 +1,67 @@ > +/* > + * Allwinner H3 Clock Control Unit emulation > + * > + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef HW_MISC_ALLWINNER_H3_CCU_H > +#define HW_MISC_ALLWINNER_H3_CCU_H > + > +#include "qemu/osdep.h" > +#include "qom/object.h" > +#include "hw/sysbus.h" > + > +/** > + * @name Constants > + * @{ > + */ > + > +/** Highest register address used by CCU device */ > +#define AW_H3_CCU_REGS_MAXADDR (0x304) > + > +/** Total number of known registers */ > +#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_REGS_MAXADDR / > sizeof(uint32_t)) > + > +/** @} */ > + > +/** > + * @name Object model > + * @{ > + */ > + > +#define TYPE_AW_H3_CCU "allwinner-h3-ccu" > +#define AW_H3_CCU(obj) \ > + OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU) > + > +/** @} */ > + > +/** > + * Allwinner H3 CCU object instance state. > + */ > +typedef struct AwH3ClockCtlState { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + /** Maps I/O registers in physical memory */ > + MemoryRegion iomem; > + > + /** Array of hardware registers */ > + uint32_t regs[AW_H3_CCU_REGS_NUM]; > + > +} AwH3ClockCtlState; > + > +#endif /* HW_MISC_ALLWINNER_H3_CCU_H */ > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > index c1ef31e875..b85edaea85 100644 > --- a/hw/arm/allwinner-h3.c > +++ b/hw/arm/allwinner-h3.c > @@ -34,6 +34,7 @@ const hwaddr allwinner_h3_memmap[] = { > [AW_H3_SRAM_A1] = 0x00000000, > [AW_H3_SRAM_A2] = 0x00044000, > [AW_H3_SRAM_C] = 0x00010000, > + [AW_H3_CCU] = 0x01c20000, > [AW_H3_PIT] = 0x01c20c00, > [AW_H3_UART0] = 0x01c28000, > [AW_H3_UART1] = 0x01c28400, > @@ -75,7 +76,6 @@ struct AwH3Unimplemented { > { "usb2", 0x01c1c000, 4 * KiB }, > { "usb3", 0x01c1d000, 4 * KiB }, > { "smc", 0x01c1e000, 4 * KiB }, > - { "ccu", 0x01c20000, 1 * KiB }, > { "pio", 0x01c20800, 1 * KiB }, > { "owa", 0x01c21000, 1 * KiB }, > { "pwm", 0x01c21400, 1 * KiB }, > @@ -170,6 +170,9 @@ static void allwinner_h3_init(Object *obj) > "clk0-freq", &error_abort); > object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), > "clk1-freq", &error_abort); > + > + sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), > + TYPE_AW_H3_CCU); > } > > static void allwinner_h3_realize(DeviceState *dev, Error **errp) > @@ -278,6 +281,10 @@ static void allwinner_h3_realize(DeviceState *dev, > Error **errp) > memory_region_add_subregion(get_system_memory(), > s->memmap[AW_H3_SRAM_C], > &s->sram_c); > > + /* Clock Control Unit */ > + qdev_init_nofail(DEVICE(&s->ccu)); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); > + > /* UART0 */ > serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, > qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), > diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c > new file mode 100644 > index 0000000000..ccf58ccdf2 > --- /dev/null > +++ b/hw/misc/allwinner-h3-ccu.c > @@ -0,0 +1,243 @@ > +/* > + * Allwinner H3 Clock Control Unit emulation > + * > + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/units.h" > +#include "hw/sysbus.h" > +#include "migration/vmstate.h" > +#include "qemu/log.h" > +#include "qemu/module.h" > +#include "hw/misc/allwinner-h3-ccu.h" > + > +/* CCU register offsets */ > +enum { > + REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */ > + REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */ > + REG_PLL_VIDEO = 0x0010, /* PLL Video Control */ > + REG_PLL_VE = 0x0018, /* PLL VE Control */ > + REG_PLL_DDR = 0x0020, /* PLL DDR Control */ > + REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */ > + REG_PLL_GPU = 0x0038, /* PLL GPU Control */ > + REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */ > + REG_PLL_DE = 0x0048, /* PLL Display Engine Control */ > + REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */ > + REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */ > + REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */ > + REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */ > + REG_MBUS = 0x00FC, /* MBUS Reset */ > + REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */ > + REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */ > + REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */ > + REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */ > + REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */ > + REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */ > + REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */ > + REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */ > + REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */ > + REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */ > + REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */ > + REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */ > + REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */ > +}; > + > +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) > + > +/* CCU register flags */ > +enum { > + REG_DRAM_CFG_UPDATE = (1 << 16), > +}; > + > +enum { > + REG_PLL_ENABLE = (1 << 31), > + REG_PLL_LOCK = (1 << 28), > +}; > + > + > +/* CCU register reset values */ > +enum { > + REG_PLL_CPUX_RST = 0x00001000, > + REG_PLL_AUDIO_RST = 0x00035514, > + REG_PLL_VIDEO_RST = 0x03006207, > + REG_PLL_VE_RST = 0x03006207, > + REG_PLL_DDR_RST = 0x00001000, > + REG_PLL_PERIPH0_RST = 0x00041811, > + REG_PLL_GPU_RST = 0x03006207, > + REG_PLL_PERIPH1_RST = 0x00041811, > + REG_PLL_DE_RST = 0x03006207, > + REG_CPUX_AXI_RST = 0x00010000, > + REG_APB1_RST = 0x00001010, > + REG_APB2_RST = 0x01000000, > + REG_DRAM_CFG_RST = 0x00000000, > + REG_MBUS_RST = 0x80000000, > + REG_PLL_TIME0_RST = 0x000000FF, > + REG_PLL_TIME1_RST = 0x000000FF, > + REG_PLL_CPUX_BIAS_RST = 0x08100200, > + REG_PLL_AUDIO_BIAS_RST = 0x10100000, > + REG_PLL_VIDEO_BIAS_RST = 0x10100000, > + REG_PLL_VE_BIAS_RST = 0x10100000, > + REG_PLL_DDR_BIAS_RST = 0x81104000, > + REG_PLL_PERIPH0_BIAS_RST = 0x10100010, > + REG_PLL_GPU_BIAS_RST = 0x10100000, > + REG_PLL_PERIPH1_BIAS_RST = 0x10100010, > + REG_PLL_DE_BIAS_RST = 0x10100000, > + REG_PLL_CPUX_TUNING_RST = 0x0A101000, > + REG_PLL_DDR_TUNING_RST = 0x14880000, > +}; > + > +static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + const AwH3ClockCtlState *s = AW_H3_CCU(opaque); > + const uint32_t idx = REG_INDEX(offset); > + > + if (idx >= AW_H3_CCU_REGS_NUM) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset > 0x%04x\n", > + __func__, (uint32_t)offset); > + return 0; > + } > + > + return s->regs[idx]; > +} > + > +static void allwinner_h3_ccu_write(void *opaque, hwaddr offset, > + uint64_t val, unsigned size) > +{ > + AwH3ClockCtlState *s = AW_H3_CCU(opaque); > + const uint32_t idx = REG_INDEX(offset); > + > + if (idx >= AW_H3_CCU_REGS_NUM) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset > 0x%04x\n", > + __func__, (uint32_t)offset); > + return; > + } > + > + switch (offset) { > + case REG_DRAM_CFG: /* DRAM Configuration */ > + val &= ~REG_DRAM_CFG_UPDATE; > + break; > + case REG_PLL_CPUX: /* PLL CPUX Control */ > + case REG_PLL_AUDIO: /* PLL Audio Control */ > + case REG_PLL_VIDEO: /* PLL Video Control */ > + case REG_PLL_VE: /* PLL VE Control */ > + case REG_PLL_DDR: /* PLL DDR Control */ > + case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */ > + case REG_PLL_GPU: /* PLL GPU Control */ > + case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */ > + case REG_PLL_DE: /* PLL Display Engine Control */ > + if (val & REG_PLL_ENABLE) { > + val |= REG_PLL_LOCK; > + } > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset > 0x%04x\n", > + __func__, (uint32_t)offset); > + break; > + } > + > + s->regs[idx] = (uint32_t) val; > +} > + > +static const MemoryRegionOps allwinner_h3_ccu_ops = { > + .read = allwinner_h3_ccu_read, > + .write = allwinner_h3_ccu_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + }, > + .impl.min_access_size = 4, > +}; > + > +static void allwinner_h3_ccu_reset(DeviceState *dev) > +{ > + AwH3ClockCtlState *s = AW_H3_CCU(dev); > + > + /* Set default values for registers */ > + s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST; > + s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST; > + s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST; > + s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST; > + s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST; > + s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST; > + s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST; > + s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST; > + s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST; > + s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST; > + s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST; > + s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST; > + s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST; > + s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST; > + s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST; > + s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST; > + s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST; > + s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST; > + s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST; > +} > + > +static void allwinner_h3_ccu_init(Object *obj) > +{ > + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > + AwH3ClockCtlState *s = AW_H3_CCU(obj); > + > + /* Memory mapping */ > + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s, > + TYPE_AW_H3_CCU, 1 * KiB); > + sysbus_init_mmio(sbd, &s->iomem); > +} > + > +static const VMStateDescription allwinner_h3_ccu_vmstate = { > + .name = "allwinner-h3-ccu", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->reset = allwinner_h3_ccu_reset; > + dc->vmsd = &allwinner_h3_ccu_vmstate; > +} > + > +static const TypeInfo allwinner_h3_ccu_info = { > + .name = TYPE_AW_H3_CCU, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_init = allwinner_h3_ccu_init, > + .instance_size = sizeof(AwH3ClockCtlState), > + .class_init = allwinner_h3_ccu_class_init, > +}; > + > +static void allwinner_h3_ccu_register(void) > +{ > + type_register_static(&allwinner_h3_ccu_info); > +} > + > +type_init(allwinner_h3_ccu_register) > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > index ba898a5781..4abd92dcee 100644 > --- a/hw/misc/Makefile.objs > +++ b/hw/misc/Makefile.objs > @@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) += macio/ > > common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o > > +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o > common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o > common-obj-$(CONFIG_NSERIES) += cbus.o > common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o > -- > 2.17.1 > >
Hi Niek, On 1/13/20 8:18 PM, Niek Linnenbank wrote: > Hi, > > Just a friendly reminder for review of this patch and the others in this > series > that don't yet have a reviewed-by tag :-) You are right to ping the list after a week. Cc'ing Damien for this particular patch, he might have good advises. Looking at the stats from your cover: include/hw/arm/allwinner-h3.h | 164 +++++ include/hw/misc/allwinner-cpucfg.h | 54 ++ include/hw/misc/allwinner-h3-ccu.h | 67 ++ include/hw/misc/allwinner-h3-dramc.h | 107 +++ include/hw/misc/allwinner-h3-sysctrl.h | 68 ++ include/hw/net/allwinner-sun8i-emac.h | 103 +++ include/hw/rtc/allwinner-rtc.h | 129 ++++ include/hw/sd/allwinner-sdhost.h | 136 ++++ hw/arm/allwinner-h3.c | 477 ++++++++++++++ hw/arm/orangepi.c | 125 ++++ hw/misc/allwinner-cpucfg.c | 282 ++++++++ hw/misc/allwinner-h3-ccu.c | 243 +++++++ hw/misc/allwinner-h3-dramc.c | 358 ++++++++++ hw/misc/allwinner-h3-sysctrl.c | 140 ++++ hw/misc/allwinner-sid.c | 170 +++++ hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++ hw/rtc/allwinner-rtc.c | 386 +++++++++++ hw/sd/allwinner-sdhost.c | 848 ++++++++++++++++++++++++ 39 files changed, 5267 insertions(+), 2 deletions(-) This is a LOT of code to process, keep in mind your series touches different subsystems with different maintainers. It is hard to know all of them in details. Since your SoC is in the same family than the A10, I've Cc'ed Beniamino Galvani. You should Cc him in your v4, hopefully he can help reviewing. Regarding the System Control Unit and SDRAM Controller, as I don't know this SoC so I have to digest the whole datasheet, so it takes me time, bare with me (I'm using my hobby time to review your work). The last patch I plan to review in your series is the SD/MMC one: 10 files changed, 1053 insertions(+), 2 deletions(-) It is 1/5th of your series in a single patch, each time I try to look at it I get scared. Anyway today I could test NetBSD booting from a SD card so I am more confident. Anyway, don't forget this comment from the New Contribution page: https://wiki.qemu.org/Contribute/SubmitAPatch#Return_the_favor Peer review only works if everyone chips in a bit of review time. If everyone submitted more patches than they reviewed, we would have a patch backlog. A good goal is to try to review at least as many patches from others as what you submit. With the quality of your patches, even if this is your first contribution, it is obvious you now understand various part of QEMU. Don't be shy to look at other patches on the list and help the community, as the reviewed authors might review you back :) That said, your series is almost there! Regards, Phil. > > Regards, > Niek
Hi Philippe, On Sat, Jan 18, 2020 at 4:37 PM Philippe Mathieu-Daudé <philmd@redhat.com> wrote: > Hi Niek, > > On 1/13/20 8:18 PM, Niek Linnenbank wrote: > > Hi, > > > > Just a friendly reminder for review of this patch and the others in this > > series > > that don't yet have a reviewed-by tag :-) > > You are right to ping the list after a week. > > Cc'ing Damien for this particular patch, he might have good advises. > > > Looking at the stats from your cover: > > include/hw/arm/allwinner-h3.h | 164 +++++ > include/hw/misc/allwinner-cpucfg.h | 54 ++ > include/hw/misc/allwinner-h3-ccu.h | 67 ++ > include/hw/misc/allwinner-h3-dramc.h | 107 +++ > include/hw/misc/allwinner-h3-sysctrl.h | 68 ++ > include/hw/net/allwinner-sun8i-emac.h | 103 +++ > include/hw/rtc/allwinner-rtc.h | 129 ++++ > include/hw/sd/allwinner-sdhost.h | 136 ++++ > hw/arm/allwinner-h3.c | 477 ++++++++++++++ > hw/arm/orangepi.c | 125 ++++ > hw/misc/allwinner-cpucfg.c | 282 ++++++++ > hw/misc/allwinner-h3-ccu.c | 243 +++++++ > hw/misc/allwinner-h3-dramc.c | 358 ++++++++++ > hw/misc/allwinner-h3-sysctrl.c | 140 ++++ > hw/misc/allwinner-sid.c | 170 +++++ > hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++ > hw/rtc/allwinner-rtc.c | 386 +++++++++++ > hw/sd/allwinner-sdhost.c | 848 ++++++++++++++++++++++++ > > 39 files changed, 5267 insertions(+), 2 deletions(-) > > This is a LOT of code to process, keep in mind your series touches > different subsystems with different maintainers. It is hard to know all > of them in details. > > Yes, true indeed. I'll be patient and wait for more feedback when it comes. > Since your SoC is in the same family than the A10, I've Cc'ed Beniamino > Galvani. You should Cc him in your v4, hopefully he can help reviewing. > > OK good idea. I'll add Beniamino in CC for v4! > Regarding the System Control Unit and SDRAM Controller, as I don't know > this SoC so I have to digest the whole datasheet, so it takes me time, > bare with me (I'm using my hobby time to review your work). > > Yes the SDRAM controller is something that needs a good read to understand it, especially also in the U-Boot sources which is using it. No hurry there, I very much appreciate all the time you already took for reviewing this series. It encourages me to continue with it as well. I'm also doing this work in my hobby time. > The last patch I plan to review in your series is the SD/MMC one: > 10 files changed, 1053 insertions(+), 2 deletions(-) > > It is 1/5th of your series in a single patch, each time I try to look at > it I get scared. Anyway today I could test NetBSD booting from a SD card > so I am more confident. > > Thanks for testing that Philippe! Yes the SD/MMC host device is indeed relatively large compared to the other patches. > Anyway, don't forget this comment from the New Contribution page: > https://wiki.qemu.org/Contribute/SubmitAPatch#Return_the_favor > > Peer review only works if everyone chips in a bit of review time. > If everyone submitted more patches than they reviewed, we would > have a patch backlog. A good goal is to try to review at least > as many patches from others as what you submit. > > With the quality of your patches, even if this is your first > contribution, it is obvious you now understand various part of QEMU. > Don't be shy to look at other patches on the list and help the > community, as the reviewed authors might review you back :) > > Thanks for reminding about that. You are right, indeed I should start reviewing other patches as well to return the favor and help others. Regards, Niek That said, your series is almost there! Regards, > > Phil. > > > > > Regards, > > Niek > >
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 4e2e6202a9..0dc18b927a 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -43,6 +43,7 @@ #include "hw/arm/boot.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" +#include "hw/misc/allwinner-h3-ccu.h" #include "target/arm/cpu.h" /** @@ -59,6 +60,7 @@ enum { AW_H3_SRAM_A1, AW_H3_SRAM_A2, AW_H3_SRAM_C, + AW_H3_CCU, AW_H3_PIT, AW_H3_UART0, AW_H3_UART1, @@ -98,6 +100,7 @@ typedef struct AwH3State { ARMCPU cpus[AW_H3_NUM_CPUS]; const hwaddr *memmap; AwA10PITState timer; + AwH3ClockCtlState ccu; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h new file mode 100644 index 0000000000..0dcb08ecd1 --- /dev/null +++ b/include/hw/misc/allwinner-h3-ccu.h @@ -0,0 +1,67 @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_MISC_ALLWINNER_H3_CCU_H +#define HW_MISC_ALLWINNER_H3_CCU_H + +#include "qemu/osdep.h" +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * @name Constants + * @{ + */ + +/** Highest register address used by CCU device */ +#define AW_H3_CCU_REGS_MAXADDR (0x304) + +/** Total number of known registers */ +#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_REGS_MAXADDR / sizeof(uint32_t)) + +/** @} */ + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_H3_CCU "allwinner-h3-ccu" +#define AW_H3_CCU(obj) \ + OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU) + +/** @} */ + +/** + * Allwinner H3 CCU object instance state. + */ +typedef struct AwH3ClockCtlState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Array of hardware registers */ + uint32_t regs[AW_H3_CCU_REGS_NUM]; + +} AwH3ClockCtlState; + +#endif /* HW_MISC_ALLWINNER_H3_CCU_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index c1ef31e875..b85edaea85 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -34,6 +34,7 @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A1] = 0x00000000, [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_CCU] = 0x01c20000, [AW_H3_PIT] = 0x01c20c00, [AW_H3_UART0] = 0x01c28000, [AW_H3_UART1] = 0x01c28400, @@ -75,7 +76,6 @@ struct AwH3Unimplemented { { "usb2", 0x01c1c000, 4 * KiB }, { "usb3", 0x01c1d000, 4 * KiB }, { "smc", 0x01c1e000, 4 * KiB }, - { "ccu", 0x01c20000, 1 * KiB }, { "pio", 0x01c20800, 1 * KiB }, { "owa", 0x01c21000, 1 * KiB }, { "pwm", 0x01c21400, 1 * KiB }, @@ -170,6 +170,9 @@ static void allwinner_h3_init(Object *obj) "clk0-freq", &error_abort); object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), "clk1-freq", &error_abort); + + sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), + TYPE_AW_H3_CCU); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -278,6 +281,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], &s->sram_c); + /* Clock Control Unit */ + qdev_init_nofail(DEVICE(&s->ccu)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* UART0 */ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c new file mode 100644 index 0000000000..ccf58ccdf2 --- /dev/null +++ b/hw/misc/allwinner-h3-ccu.c @@ -0,0 +1,243 @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/allwinner-h3-ccu.h" + +/* CCU register offsets */ +enum { + REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */ + REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */ + REG_PLL_VIDEO = 0x0010, /* PLL Video Control */ + REG_PLL_VE = 0x0018, /* PLL VE Control */ + REG_PLL_DDR = 0x0020, /* PLL DDR Control */ + REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */ + REG_PLL_GPU = 0x0038, /* PLL GPU Control */ + REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */ + REG_PLL_DE = 0x0048, /* PLL Display Engine Control */ + REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */ + REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */ + REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */ + REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */ + REG_MBUS = 0x00FC, /* MBUS Reset */ + REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */ + REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */ + REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */ + REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */ + REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */ + REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */ + REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */ + REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */ + REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */ + REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */ + REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */ + REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */ + REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */ +}; + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* CCU register flags */ +enum { + REG_DRAM_CFG_UPDATE = (1 << 16), +}; + +enum { + REG_PLL_ENABLE = (1 << 31), + REG_PLL_LOCK = (1 << 28), +}; + + +/* CCU register reset values */ +enum { + REG_PLL_CPUX_RST = 0x00001000, + REG_PLL_AUDIO_RST = 0x00035514, + REG_PLL_VIDEO_RST = 0x03006207, + REG_PLL_VE_RST = 0x03006207, + REG_PLL_DDR_RST = 0x00001000, + REG_PLL_PERIPH0_RST = 0x00041811, + REG_PLL_GPU_RST = 0x03006207, + REG_PLL_PERIPH1_RST = 0x00041811, + REG_PLL_DE_RST = 0x03006207, + REG_CPUX_AXI_RST = 0x00010000, + REG_APB1_RST = 0x00001010, + REG_APB2_RST = 0x01000000, + REG_DRAM_CFG_RST = 0x00000000, + REG_MBUS_RST = 0x80000000, + REG_PLL_TIME0_RST = 0x000000FF, + REG_PLL_TIME1_RST = 0x000000FF, + REG_PLL_CPUX_BIAS_RST = 0x08100200, + REG_PLL_AUDIO_BIAS_RST = 0x10100000, + REG_PLL_VIDEO_BIAS_RST = 0x10100000, + REG_PLL_VE_BIAS_RST = 0x10100000, + REG_PLL_DDR_BIAS_RST = 0x81104000, + REG_PLL_PERIPH0_BIAS_RST = 0x10100010, + REG_PLL_GPU_BIAS_RST = 0x10100000, + REG_PLL_PERIPH1_BIAS_RST = 0x10100010, + REG_PLL_DE_BIAS_RST = 0x10100000, + REG_PLL_CPUX_TUNING_RST = 0x0A101000, + REG_PLL_DDR_TUNING_RST = 0x14880000, +}; + +static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3ClockCtlState *s = AW_H3_CCU(opaque); + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_CCU_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return s->regs[idx]; +} + +static void allwinner_h3_ccu_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3ClockCtlState *s = AW_H3_CCU(opaque); + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_CCU_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + switch (offset) { + case REG_DRAM_CFG: /* DRAM Configuration */ + val &= ~REG_DRAM_CFG_UPDATE; + break; + case REG_PLL_CPUX: /* PLL CPUX Control */ + case REG_PLL_AUDIO: /* PLL Audio Control */ + case REG_PLL_VIDEO: /* PLL Video Control */ + case REG_PLL_VE: /* PLL VE Control */ + case REG_PLL_DDR: /* PLL DDR Control */ + case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */ + case REG_PLL_GPU: /* PLL GPU Control */ + case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */ + case REG_PLL_DE: /* PLL Display Engine Control */ + if (val & REG_PLL_ENABLE) { + val |= REG_PLL_LOCK; + } + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } + + s->regs[idx] = (uint32_t) val; +} + +static const MemoryRegionOps allwinner_h3_ccu_ops = { + .read = allwinner_h3_ccu_read, + .write = allwinner_h3_ccu_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static void allwinner_h3_ccu_reset(DeviceState *dev) +{ + AwH3ClockCtlState *s = AW_H3_CCU(dev); + + /* Set default values for registers */ + s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST; + s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST; + s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST; + s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST; + s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST; + s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST; + s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST; + s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST; + s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST; + s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST; + s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST; + s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST; + s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST; + s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST; + s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST; + s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST; +} + +static void allwinner_h3_ccu_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3ClockCtlState *s = AW_H3_CCU(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s, + TYPE_AW_H3_CCU, 1 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_ccu_vmstate = { + .name = "allwinner-h3-ccu", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_ccu_reset; + dc->vmsd = &allwinner_h3_ccu_vmstate; +} + +static const TypeInfo allwinner_h3_ccu_info = { + .name = TYPE_AW_H3_CCU, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_ccu_init, + .instance_size = sizeof(AwH3ClockCtlState), + .class_init = allwinner_h3_ccu_class_init, +}; + +static void allwinner_h3_ccu_register(void) +{ + type_register_static(&allwinner_h3_ccu_info); +} + +type_init(allwinner_h3_ccu_register) diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781..4abd92dcee 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
The Clock Control Unit is responsible for clock signal generation, configuration and distribution in the Allwinner H3 System on Chip. This commit adds support for the Clock Control Unit which emulates a simple read/write register interface. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> --- include/hw/arm/allwinner-h3.h | 3 + include/hw/misc/allwinner-h3-ccu.h | 67 ++++++++ hw/arm/allwinner-h3.c | 9 +- hw/misc/allwinner-h3-ccu.c | 243 +++++++++++++++++++++++++++++ hw/misc/Makefile.objs | 1 + 5 files changed, 322 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/allwinner-h3-ccu.h create mode 100644 hw/misc/allwinner-h3-ccu.c