Message ID | 149943131289.8972.14899352517803578316.stgit@frigg.lan |
---|---|
State | New |
Headers | show |
Lluís Vilanova <vilanova@ac.upc.edu> writes: > Incrementally paves the way towards using the generic instruction translation > loop. > > Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> > Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/translate-a64.c | 36 ++++++++++++++++++++++-------------- > 1 file changed, 22 insertions(+), 14 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 4270ac3847..5c04ff3d8b 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -11190,21 +11190,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) > free_tmp_a64(s); > } > > -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, > - TranslationBlock *tb) > +static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, > + CPUState *cpu) > { > - CPUARMState *env = cs->env_ptr; > - ARMCPU *cpu = arm_env_get_cpu(env); > DisasContext *dc = container_of(dcbase, DisasContext, base); > - target_ulong next_page_start; > - int max_insns; > - > - dc->base.tb = tb; > - dc->base.pc_first = dc->base.tb->pc; > - dc->base.pc_next = dc->base.pc_first; > - dc->base.is_jmp = DISAS_NEXT; > - dc->base.num_insns = 0; > - dc->base.singlestep_enabled = cs->singlestep_enabled; > + CPUARMState *env = cpu->env_ptr; > + ARMCPU *arm_cpu = arm_env_get_cpu(env); > > dc->pc = dc->base.pc_first; > dc->condjmp = 0; > @@ -11230,7 +11221,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, > dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); > dc->vec_len = 0; > dc->vec_stride = 0; > - dc->cp_regs = cpu->cp_regs; > + dc->cp_regs = arm_cpu->cp_regs; > dc->features = env->features; > > /* Single step state. The code-generation logic here is: > @@ -11254,6 +11245,23 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, > dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); > > init_tmp_a64_array(dc); > +} > + > +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, > + TranslationBlock *tb) > +{ > + CPUARMState *env = cs->env_ptr; > + DisasContext *dc = container_of(dcbase, DisasContext, base); > + target_ulong next_page_start; > + int max_insns; > + > + dc->base.tb = tb; > + dc->base.pc_first = dc->base.tb->pc; > + dc->base.pc_next = dc->base.pc_first; > + dc->base.is_jmp = DISAS_NEXT; > + dc->base.num_insns = 0; > + dc->base.singlestep_enabled = cs->singlestep_enabled; > + aarch64_tr_init_disas_context(&dc->base, cs); > > next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; > max_insns = dc->base.tb->cflags & CF_COUNT_MASK; -- Alex Bennée
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4270ac3847..5c04ff3d8b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11190,21 +11190,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) free_tmp_a64(s); } -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) +static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { - CPUARMState *env = cs->env_ptr; - ARMCPU *cpu = arm_env_get_cpu(env); DisasContext *dc = container_of(dcbase, DisasContext, base); - target_ulong next_page_start; - int max_insns; - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; + CPUARMState *env = cpu->env_ptr; + ARMCPU *arm_cpu = arm_env_get_cpu(env); dc->pc = dc->base.pc_first; dc->condjmp = 0; @@ -11230,7 +11221,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len = 0; dc->vec_stride = 0; - dc->cp_regs = cpu->cp_regs; + dc->cp_regs = arm_cpu->cp_regs; dc->features = env->features; /* Single step state. The code-generation logic here is: @@ -11254,6 +11245,23 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); init_tmp_a64_array(dc); +} + +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) +{ + CPUARMState *env = cs->env_ptr; + DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong next_page_start; + int max_insns; + + dc->base.tb = tb; + dc->base.pc_first = dc->base.tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cs->singlestep_enabled; + aarch64_tr_init_disas_context(&dc->base, cs); next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = dc->base.tb->cflags & CF_COUNT_MASK;