diff mbox

[alsa-devel] Setting some clocks back to DUMMY fixes spdif output on imx6q wandboard rev B1

Message ID CAOMZO5AoCo9Faq7oWgRQUE0Hg+Pg+i6z8eg-qeLFDvwpoEqz_g@mail.gmail.com (mailing list archive)
State Not Applicable
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Commit Message

Fabio Estevam Aug. 31, 2016, 1:11 p.m. UTC 
Hi Xavi/Nicolin,

On Wed, Aug 31, 2016 at 6:10 AM, Xavi Drudis Ferran <xdrudis@tinet.cat> wrote:
> El Tue, Aug 30, 2016 at 09:21:01PM -0700, Nicolin Chen deia:
>>
>> No, the problem is not at the rate but the source -- Although the
>> MLB clock exists in the clock tree as a better rate provider, it
>> might not be correctly enabled or running at the rate it claims.
>>
>
>>
>> There are five MLB clocks sharing the same clock gate according
>> to CCM chapter in the Reference Manual of imx6q. But five clocks
>> come from three different parent clocks, and I am wondering if
>> the MLB clock that's connected to the S/PDIF module is really
>> derived from this AXI.
>>
>> Hope Fabio might be able to help on the clock tree issue here:)
>>
>
> I hope too, it's a little over my head, to be euphemistic.
>
>>
>> Another solution for you could be to change the rates of two of
>> those existing clocks to the perfect rates for 44.1KHz and 48KHz
>> respectively, 22579200Hz and 24576000Hz for example. (If you
>> only need one sample rate support, changing rxtx1 SPDIF clock
>> only then.)
>
> Thank you very much.  I'm not sure what practical problem that would
> solve for me, audio sounds quite right to my ears with the workaround
> (disabling MLB). I've looked page 121 of
> http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQIEC.pdf
> And it seems like the the margin for the SPDIF clock would be 16 ns
> and I'm like 10 times out of spec. But I can't hear the problem.  I
> may try it one day to hear how it sounds.
>
> I'll try to remember it if I ever come across some problem with my audio.
> For now what I'd like is to stay as close to linux-libre mainline
> as possible, so the quick workaround is enough for me.
>
> Now for the general case, I'm not sure what the solution should be.
> Page 4 of the pdf above says MLB is not present in industrial "parts",
> only automotive, or consumer "parts". There are several versions of
> IMX6Q in the market.  What version must I have ? I guess consumer
> (with MLB) but I'm not sure... According to the wandboard-quad-rev-b1
> manual its consumer, MCIMX6Q5EYM10AC, so I should have MLB, I guess.
>
> $ cat /proc/cpuinfo
> processor          : 0
> model name         : ARMv7 Processor rev 10 (v7l)
> BogoMIPS           : 7.54
> Features           : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
> CPU implementer    : 0x41
> CPU architecture: 7
> CPU variant       : 0x2
> CPU part          : 0xc09
> CPU revision      : 10
> [...]
>
> I can't tell what CPU part : 0xc09 means.
>
> In the reference manual pg 796 I see the same gate seems to affect Media
> Local Bus (MLB) clock and Digital Transmission Content Protection
> (DTCP). I don't use DTCP but I haven't done anything to disable it.
>
> http://www.nxp.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf?fasp=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf

Sorry for the delay.

As far as I can see, there are two current issues:

1. Regression caused by: 833f2cbf7091099bae ("ARM: dts: imx6: change
the core clock of spdif").

Looks like that this commit did much more than just changing the core
clock of spdif.

It does not mention why MLB clock has been added. Looking at MX6Q RM I
do not see the connection between MLB and SPDIF.

So I agree with Xavi's suggestion of using the dummy_clk instead of mlb clock.

Xavi,

Care to send a formal patch with your change?

2. SPDIF clock rate not accurate. Probably using PLL4 as SPDIF source
would help to get more accurate SPDIF clock rates.

Could you please try the untested change?


        /* All existing boards with PCIe use LVDS1 */
        if (IS_ENABLED(CONFIG_PCI_IMX6))

Regards,

Fabio Estevam

Comments

Fabio Estevam Aug. 31, 2016, 1:30 p.m. UTC | #1 
Xavi,

On Wed, Aug 31, 2016 at 10:11 AM, Fabio Estevam <festevam@gmail.com> wrote:

> Xavi,
>
> Care to send a formal patch with your change?

If you prefer, I can send this change to the ARM kernel mailing list.

Please let me know what you prefer.

Thanks
Xavier Drudis Ferran Aug. 31, 2016, 1:47 p.m. UTC | #2 
El Wed, Aug 31, 2016 at 10:30:25AM -0300, Fabio Estevam deia:
> Xavi,
> 
> On Wed, Aug 31, 2016 at 10:11 AM, Fabio Estevam <festevam@gmail.com> wrote:
> 
> > Xavi,
> >
> > Care to send a formal patch with your change?
> 
> If you prefer, I can send this change to the ARM kernel mailing list.
>

Whatever is easier for you. I'll have to look up the formalities for
sending the patch myself (format, copyright, where to send, etc.)
since I've never sent a patch for linux. I don't believe such a simple
change can be copyrightable, but the original isn't mine, it's from
that URL I gave, https://community.nxp.com/thread/387131 so originally
from ambika@iwavesystems.com

> Please let me know what you prefer.
>

If it's easy for you to send it yourself, I would prefer so and I'm
grateful. If not, it'll be an exercise for me, no problem.
Xavier Drudis Ferran Aug. 31, 2016, 1:49 p.m. UTC | #3 
El Wed, Aug 31, 2016 at 10:11:13AM -0300, Fabio Estevam deia:
> 2. SPDIF clock rate not accurate. Probably using PLL4 as SPDIF source
> would help to get more accurate SPDIF clock rates.
> 
> Could you please try the untested change?
> 
> --- a/drivers/clk/imx/clk-imx6q.c
> +++ b/drivers/clk/imx/clk-imx6q.c
> @@ -623,7 +623,7 @@ static void __init imx6q_clocks_init(struct
> device_node *ccm_node)
>                 pr_warn("failed to set up CLKO: %d\n", ret);
> 
>         /* Audio-related clocks configuration */
> -       clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL],
> clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
> +       clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL],
> clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);
> 
>         /* All existing boards with PCIe use LVDS1 */
>         if (IS_ENABLED(CONFIG_PCI_IMX6))
>

I'm going to try. I'll take a while. I'll report the result later.

Thank you very much.
Fabio Estevam Aug. 31, 2016, 2:02 p.m. UTC | #4 
Hi Xavi,

On Wed, Aug 31, 2016 at 10:47 AM, Xavi Drudis Ferran <xdrudis@tinet.cat> wrote:

> If it's easy for you to send it yourself, I would prefer so and I'm
> grateful. If not, it'll be an exercise for me, no problem.

I have just submitted the patch with you on Cc.

If you could reply to it with your Tested-by tag, that would be great.

Thanks
Xavier Drudis Ferran Aug. 31, 2016, 5:49 p.m. UTC | #5 
El Wed, Aug 31, 2016 at 03:49:25PM +0200, Xavi Drudis Ferran deia:
> El Wed, Aug 31, 2016 at 10:11:13AM -0300, Fabio Estevam deia:
> > 2. SPDIF clock rate not accurate. Probably using PLL4 as SPDIF source
> > would help to get more accurate SPDIF clock rates.
> > 
> > Could you please try the untested change?
> > 
> > --- a/drivers/clk/imx/clk-imx6q.c
> > +++ b/drivers/clk/imx/clk-imx6q.c
> > @@ -623,7 +623,7 @@ static void __init imx6q_clocks_init(struct
> > device_node *ccm_node)
> >                 pr_warn("failed to set up CLKO: %d\n", ret);
> > 
> >         /* Audio-related clocks configuration */
> > -       clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL],
> > clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
> > +       clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL],
> > clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);
> > 
> >         /* All existing boards with PCIe use LVDS1 */
> >         if (IS_ENABLED(CONFIG_PCI_IMX6))
> >
> 
> I'm going to try. I'll take a while. I'll report the result later.
> 
> Thank you very much.

I just tried. Spdif output still works. I can't hear any difference. 

I've summarised the tests in a table:

Nominal    
Hz               32000      44100      48000      96000     192000
ns               31250      22676      20833      10417       5208

Linux-libre-4.7 (unchanged)   (no spdif output)                                                               
Hz               32226      43882      47965      95930     196428
ns               31031      22788      20849      10424       5091
deviation(ns)      219       -113        -15         -8        117

only core (SPDIF_GCLK), rxtx0 (CLK_OSC), rxtx1(SPDIF) & spba (spdif output)
Hz               31719      43859      47368      94736     187500
ns               31527      22800      21111      10556       5333
deviation(ns)     -277       -125       -278       -139       -125
 
without MLB (the rest  unchanged)   (spdif output)                         
Hz               32226      43859      47368      94736     187500
ns               31031      22800      21111      10556       5333
deviation(ns)      219       -125       -278       -139       -125

without MLB, and PLL4 instead of PLL3 for SPDIF (spdif output)               
Hz               32226      44836      49107      93750     187500
ns               31031      22304      20364      10667       5333
deviation(ns)      219        372        470       -250       -125

I saw page 121 of
http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQIEC.pdf
And it seems like the the margin for the SPDIF clock would be 16 ns
so I've just inverted the frequencies to compare, but I'm not convinced
it's relevant. 

Here's the extract from dmesg with your patch (and .dtsi like mainline
except MLB replaced with DUMMY).

[...]
[    7.517394] etnaviv-gpu 130000.gpu: model: GC2000, revision: 5108
[    7.578089] imx_thermal 2000000.aips-bus:tempmon: Extended Commercial CPU temperature grade - max:105C critical:100C passive:95C
[    7.594443] etnaviv-gpu 2204000.gpu: model: GC355, revision: 1215
[    7.594454] etnaviv-gpu 2204000.gpu: Ignoring GPU with VG and FE2.0
[    7.594459] etnaviv-gpu 2204000.gpu: hw init failed: -6
[    7.653041] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe
[    7.656319] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    7.704159] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 32000Hz sample rate
[    7.711719] fsl-spdif-dai 2004000.spdif: use txclk df 16 for 32000Hz sample rate
[    7.718328] fsl-spdif-dai 2004000.spdif: use sysclk df 2 for 32000Hz sample rate
[    7.724762] fsl-spdif-dai 2004000.spdif: the best rate for 32000Hz sample rate is 32226Hz
[    7.732679] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    7.760087] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 44100Hz sample rate
[    7.766536] fsl-spdif-dai 2004000.spdif: use txclk df 1 for 44100Hz sample rate
[    7.772986] fsl-spdif-dai 2004000.spdif: use sysclk df 23 for 44100Hz sample rate
[    7.780120] fsl-spdif-dai 2004000.spdif: the best rate for 44100Hz sample rate is 44836Hz
[    7.788952] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    7.825238] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 48000Hz sample rate
[    7.831515] fsl-spdif-dai 2004000.spdif: use txclk df 7 for 48000Hz sample rate
[    7.837583] fsl-spdif-dai 2004000.spdif: use sysclk df 3 for 48000Hz sample rate
[    7.843718] fsl-spdif-dai 2004000.spdif: the best rate for 48000Hz sample rate is 49107Hz
[    7.849672] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    7.878632] fsl-spdif-dai 2004000.spdif: use rxtx0 as tx clock source for 96000Hz sample rate
[    7.884550] fsl-spdif-dai 2004000.spdif: use txclk df 4 for 96000Hz sample rate
[    7.890390] fsl-spdif-dai 2004000.spdif: the best rate for 96000Hz sample rate is 93750Hz
[    7.896253] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    7.921228] fsl-spdif-dai 2004000.spdif: use rxtx0 as tx clock source for 192000Hz sample rate
[    7.927034] fsl-spdif-dai 2004000.spdif: use txclk df 2 for 192000Hz sample rate
[    7.932809] fsl-spdif-dai 2004000.spdif: the best rate for 192000Hz sample rate is 187500Hz
[    7.938616] fsl-spdif-dai 2004000.spdif: imx_pcm_dma_init failed: -517
[    7.944791] fsl-ssi-dai 2028000.ssi: No cache defaults, reading back from HW
[    7.954697] fsl-asrc 2034000.asrc: driver registered
[    7.961411] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe
[    7.967622] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    7.992427] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 32000Hz sample rate
[    7.998228] fsl-spdif-dai 2004000.spdif: use txclk df 16 for 32000Hz sample rate
[    8.004122] fsl-spdif-dai 2004000.spdif: use sysclk df 2 for 32000Hz sample rate
[    8.009806] fsl-spdif-dai 2004000.spdif: the best rate for 32000Hz sample rate is 32226Hz
[    8.015572] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    8.044534] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 44100Hz sample rate
[    8.050294] fsl-spdif-dai 2004000.spdif: use txclk df 1 for 44100Hz sample rate
[    8.056069] fsl-spdif-dai 2004000.spdif: use sysclk df 23 for 44100Hz sample rate
[    8.061869] fsl-spdif-dai 2004000.spdif: the best rate for 44100Hz sample rate is 44836Hz
[    8.067662] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    8.092093] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 48000Hz sample rate
[    8.097916] fsl-spdif-dai 2004000.spdif: use txclk df 7 for 48000Hz sample rate
[    8.103769] fsl-spdif-dai 2004000.spdif: use sysclk df 3 for 48000Hz sample rate
[    8.109660] fsl-spdif-dai 2004000.spdif: the best rate for 48000Hz sample rate is 49107Hz
[    8.115488] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    8.141250] fsl-spdif-dai 2004000.spdif: use rxtx0 as tx clock source for 96000Hz sample rate
[    8.147179] fsl-spdif-dai 2004000.spdif: use txclk df 4 for 96000Hz sample rate
[    8.153066] fsl-spdif-dai 2004000.spdif: the best rate for 96000Hz sample rate is 93750Hz
[    8.158900] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    8.185506] fsl-spdif-dai 2004000.spdif: use rxtx0 as tx clock source for 192000Hz sample rate
[    8.191441] fsl-spdif-dai 2004000.spdif: use txclk df 2 for 192000Hz sample rate
[    8.197297] fsl-spdif-dai 2004000.spdif: the best rate for 192000Hz sample rate is 187500Hz
[    8.203477] fsl-spdif-dai 2004000.spdif: imx_pcm_dma_init failed: -517
[    8.210220] fsl-ssi-dai 2028000.ssi: No cache defaults, reading back from HW
[    8.653296] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe
[    8.678782] imx-spdif sound-spdif: ASoC: CPU DAI (null) not registered
[    8.682393] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    8.705822] imx-spdif sound-spdif: snd_soc_register_card failed: -517
[    8.735316] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 32000Hz sample rate
[    8.741460] fsl-spdif-dai 2004000.spdif: use txclk df 16 for 32000Hz sample rate
[    8.747889] fsl-spdif-dai 2004000.spdif: use sysclk df 2 for 32000Hz sample rate
[    8.754006] fsl-spdif-dai 2004000.spdif: the best rate for 32000Hz sample rate is 32226Hz
[    8.755063] sgtl5000 1-000a: sgtl5000 revision 0x11
[...]
[    8.776463] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    8.804281] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 44100Hz sample rate
[    8.810549] fsl-spdif-dai 2004000.spdif: use txclk df 1 for 44100Hz sample rate
[    8.816670] fsl-spdif-dai 2004000.spdif: use sysclk df 23 for 44100Hz sample rate
[    8.822881] fsl-spdif-dai 2004000.spdif: the best rate for 44100Hz sample rate is 44836Hz
[    8.829149] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    8.857633] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 48000Hz sample rate
[    8.864664] fsl-spdif-dai 2004000.spdif: use txclk df 7 for 48000Hz sample rate
[    8.871299] fsl-spdif-dai 2004000.spdif: use sysclk df 3 for 48000Hz sample rate
[    8.878169] fsl-spdif-dai 2004000.spdif: the best rate for 48000Hz sample rate is 49107Hz
[    8.885341] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    8.887272] 20ec000.sdma: Missing Free firmware (non-Free firmware loading is disabled)
[    8.887325] imx-sdma 20ec000.sdma: failed to get firmware from device tree
[    8.928411] fsl-spdif-dai 2004000.spdif: use rxtx0 as tx clock source for 96000Hz sample rate
[    8.932841] imx-sdma 20ec000.sdma: Direct firmware load for /*(DEBLOBBED)*/ failed with error -2
[    8.941518] fsl-spdif-dai 2004000.spdif: use txclk df 4 for 96000Hz sample rate
[    8.948104] fsl-spdif-dai 2004000.spdif: the best rate for 96000Hz sample rate is 93750Hz
[    8.954948] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    8.985543] fsl-spdif-dai 2004000.spdif: use rxtx0 as tx clock source for 192000Hz sample rate
[    8.992121] fsl-spdif-dai 2004000.spdif: use txclk df 2 for 192000Hz sample rate
[    8.998731] fsl-spdif-dai 2004000.spdif: the best rate for 192000Hz sample rate is 187500Hz
[...]
[    9.013319] fsl-spdif-dai 2004000.spdif: imx_pcm_dma_init failed: -517
[    9.029511] fsl-ssi-dai 2028000.ssi: No cache defaults, reading back from HW
[    9.052247] imx-spdif sound-spdif: ASoC: CPU DAI (null) not registered
[    9.061522] imx-spdif sound-spdif: snd_soc_register_card failed: -517
[    9.072088] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe
[    9.087019] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    9.120952] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 32000Hz sample rate
[    9.128069] fsl-spdif-dai 2004000.spdif: use txclk df 16 for 32000Hz sample rate
[    9.135255] fsl-spdif-dai 2004000.spdif: use sysclk df 2 for 32000Hz sample rate
[    9.142316] fsl-spdif-dai 2004000.spdif: the best rate for 32000Hz sample rate is 32226Hz
[    9.149247] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    9.181927] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 44100Hz sample rate
[    9.188687] sgtl5000 1-000a: Using internal LDO instead of VDDD
[    9.196207] fsl-spdif-dai 2004000.spdif: use txclk df 1 for 44100Hz sample rate
[    9.203005] fsl-spdif-dai 2004000.spdif: use sysclk df 23 for 44100Hz sample rate
[    9.209998] fsl-spdif-dai 2004000.spdif: the best rate for 44100Hz sample rate is 44836Hz
[    9.216928] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    9.250153] fsl-spdif-dai 2004000.spdif: use rxtx5 as tx clock source for 48000Hz sample rate
[    9.256987] fsl-spdif-dai 2004000.spdif: use txclk df 7 for 48000Hz sample rate
[    9.263890] fsl-spdif-dai 2004000.spdif: use sysclk df 3 for 48000Hz sample rate
[    9.270641] fsl-spdif-dai 2004000.spdif: the best rate for 48000Hz sample rate is 49107Hz
[    9.277343] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    9.305524] fsl-spdif-dai 2004000.spdif: use rxtx0 as tx clock source for 96000Hz sample rate
[    9.312400] fsl-spdif-dai 2004000.spdif: use txclk df 4 for 96000Hz sample rate
[    9.319041] fsl-spdif-dai 2004000.spdif: the best rate for 96000Hz sample rate is 93750Hz
[    9.325799] fsl-spdif-dai 2004000.spdif: enter fsl_spdif_probe_txclk
[    9.354693] fsl-asoc-card sound: sgtl5000 <-> 2028000.ssi mapping ok
[    9.357288] fsl-spdif-dai 2004000.spdif: use rxtx0 as tx clock source for 192000Hz sample rate
[    9.357293] fsl-spdif-dai 2004000.spdif: use txclk df 2 for 192000Hz sample rate
[    9.357298] fsl-spdif-dai 2004000.spdif: the best rate for 192000Hz sample rate is 187500Hz
[    9.470268] imx-spdif sound-spdif: snd-soc-dummy-dai <-> 2004000.spdif mapping ok
[...]
[   71.548012] fsl-spdif-dai 2004000.spdif: expected clock rate = 64915200
[   71.548027] fsl-spdif-dai 2004000.spdif: actual clock rate = 66000000
[   71.548043] fsl-spdif-dai 2004000.spdif: set sample rate to 44836Hz for 44100Hz playback
[   71.548054] fsl-spdif-dai 2004000.spdif: STCSCH: 0x304000
[   71.548065] fsl-spdif-dai 2004000.spdif: STCSCL: 0x000000
[   71.743796] fsl-spdif-dai 2004000.spdif: expected clock rate = 64915200
[   71.743812] fsl-spdif-dai 2004000.spdif: actual clock rate = 66000000
[   71.743823] fsl-spdif-dai 2004000.spdif: set sample rate to 44836Hz for 44100Hz playback
[   71.743844] fsl-spdif-dai 2004000.spdif: STCSCH: 0x304000
[   71.743867] fsl-spdif-dai 2004000.spdif: STCSCL: 0x000000

And when playing sound (spdif output works ok)

[  128.778530] fsl-spdif-dai 2004000.spdif: expected clock rate = 64915200
[  128.778549] fsl-spdif-dai 2004000.spdif: actual clock rate = 66000000
[  128.778560] fsl-spdif-dai 2004000.spdif: set sample rate to 44836Hz for 44100Hz playback
[  128.778575] fsl-spdif-dai 2004000.spdif: STCSCH: 0x304000
[  128.778583] fsl-spdif-dai 2004000.spdif: STCSCL: 0x000000


Thank you amd feel free to suggest more tests, but it is good enough
as it is for me.
Fabio Estevam Aug. 31, 2016, 6:02 p.m. UTC | #6 
On Wed, Aug 31, 2016 at 2:49 PM, Xavi Drudis Ferran <xdrudis@tinet.cat> wrote:

> Thank you amd feel free to suggest more tests, but it is good enough
> as it is for me.

Ok, thanks for trying. So let's keep the SPDIF parent clock as is.
diff mbox

Patch

--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -623,7 +623,7 @@  static void __init imx6q_clocks_init(struct
device_node *ccm_node)
                pr_warn("failed to set up CLKO: %d\n", ret);

        /* Audio-related clocks configuration */
-       clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL],
clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
+       clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL],
clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);