target-tilegx: Check zero dest register for ld instructions

From: Chen Gang <gang.chen.5i5j@gmail.com>

At present, qemu x86_64 host backend can not remove the related dummy
instructions. Even the worse, sometimes, it will generate the incorrect
instructions which will cause segment fault for prefetch_l3 instruction.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
---
 target-tilegx/translate.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

On 09/28/2015 11:51 PM, gang.chen.5i5j@gmail.com wrote:
> From: Chen Gang <gang.chen.5i5j@gmail.com>
>
> At present, qemu x86_64 host backend can not remove the related dummy
> instructions. Even the worse, sometimes, it will generate the incorrect
> instructions which will cause segment fault for prefetch_l3 instruction.
>
> Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
> ---
>   target-tilegx/translate.c | 10 +++++++---
>   1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 86da6b5..7232361 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -620,7 +620,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>           memop = MO_TEQ;
>           mnemonic = "ld";
>       do_load:
> -        tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
> +        if (dest != TILEGX_R_ZERO) {
> +            tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
> +        }

This isn't right.  Not all load instructions are nofault prefetches.


r~


>           break;
>       case OE_RR_X1(LDNA):
>           tcg_gen_andi_tl(tdest, tsrca, ~7);
> @@ -1987,8 +1989,10 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
>           memop = MO_TEQ;
>           mnemonic = "ld";
>       do_load:
> -        tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
> -                           dc->mmuidx, memop);
> +        if (srcbdest != TILEGX_R_ZERO) {
> +            tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
> +                               dc->mmuidx, memop);
> +        }
>           qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
>                         reg_names[srcbdest], reg_names[srca]);
>           return TILEGX_EXCP_NONE;
>

On 10/1/15 10:29, Richard Henderson wrote:
> On 09/28/2015 11:51 PM, gang.chen.5i5j@gmail.com wrote:
>> From: Chen Gang <gang.chen.5i5j@gmail.com>
>>
>> At present, qemu x86_64 host backend can not remove the related dummy
>> instructions. Even the worse, sometimes, it will generate the incorrect
>> instructions which will cause segment fault for prefetch_l3 instruction.
>>
>> Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
>> ---
>> target-tilegx/translate.c | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
>> index 86da6b5..7232361 100644
>> --- a/target-tilegx/translate.c
>> +++ b/target-tilegx/translate.c
>> @@ -620,7 +620,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>> memop = MO_TEQ;
>> mnemonic = "ld";
>> do_load:
>> - tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
>> + if (dest != TILEGX_R_ZERO) {
>> + tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
>> + }
>
> This isn't right. Not all load instructions are nofault prefetches.
>

OK, thanks.

--
Chen Gang (陈刚)

Open, share, and attitude like air, water, and life which God blessed