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[for-2.5,23/30] m68k: add linkl

Message ID 1439151229-27747-24-git-send-email-laurent@vivier.eu
State New
Headers show

Commit Message

Laurent Vivier Aug. 9, 2015, 8:13 p.m. UTC
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/translate.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

Comments

Richard Henderson Aug. 12, 2015, 5:33 p.m. UTC | #1
On 08/09/2015 01:13 PM, Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
>  target-m68k/translate.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/target-m68k/translate.c b/target-m68k/translate.c
> index 9a7558a..95d58d1 100644
> --- a/target-m68k/translate.c
> +++ b/target-m68k/translate.c
> @@ -1789,8 +1789,24 @@ DISAS_INSN(link)
>      TCGv reg;
>      TCGv tmp;
>  
> -    offset = cpu_ldsw_code(env, s->pc);
> -    s->pc += 2;
> +    offset = read_im16(env, s);
> +    reg = AREG(insn, 0);
> +    tmp = tcg_temp_new();
> +    tcg_gen_subi_i32(tmp, QREG_SP, 4);
> +    gen_store(s, OS_LONG, tmp, reg);
> +    if ((insn & 7) != 7) {
> +        tcg_gen_mov_i32(reg, tmp);
> +    }
> +    tcg_gen_addi_i32(QREG_SP, tmp, offset);
> +}
> +
> +DISAS_INSN(linkl)
> +{
> +    int32_t offset;
> +    TCGv reg;
> +    TCGv tmp;
> +
> +    offset = read_im32(env, s);
>      reg = AREG(insn, 0);
>      tmp = tcg_temp_new();
>      tcg_gen_subi_i32(tmp, QREG_SP, 4);

Surely you can share most of the code via a subroutine,
since the only difference is the size of the immediate.

> @@ -3179,6 +3195,7 @@ void register_m68k_insns (CPUM68KState *env)
>      INSN(not,       4600, ff00, M68000);
>      INSN(undef,     46c0, ffc0, M68000);
>      INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
> +    INSN(linkl,     4808, fff8, M68000);
>      INSN(pea,       4840, ffc0, CF_ISA_A);
>      INSN(pea,       4840, ffc0, M68000);
>      INSN(swap,      4840, fff8, CF_ISA_A);
>
diff mbox

Patch

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 9a7558a..95d58d1 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1789,8 +1789,24 @@  DISAS_INSN(link)
     TCGv reg;
     TCGv tmp;
 
-    offset = cpu_ldsw_code(env, s->pc);
-    s->pc += 2;
+    offset = read_im16(env, s);
+    reg = AREG(insn, 0);
+    tmp = tcg_temp_new();
+    tcg_gen_subi_i32(tmp, QREG_SP, 4);
+    gen_store(s, OS_LONG, tmp, reg);
+    if ((insn & 7) != 7) {
+        tcg_gen_mov_i32(reg, tmp);
+    }
+    tcg_gen_addi_i32(QREG_SP, tmp, offset);
+}
+
+DISAS_INSN(linkl)
+{
+    int32_t offset;
+    TCGv reg;
+    TCGv tmp;
+
+    offset = read_im32(env, s);
     reg = AREG(insn, 0);
     tmp = tcg_temp_new();
     tcg_gen_subi_i32(tmp, QREG_SP, 4);
@@ -3179,6 +3195,7 @@  void register_m68k_insns (CPUM68KState *env)
     INSN(not,       4600, ff00, M68000);
     INSN(undef,     46c0, ffc0, M68000);
     INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
+    INSN(linkl,     4808, fff8, M68000);
     INSN(pea,       4840, ffc0, CF_ISA_A);
     INSN(pea,       4840, ffc0, M68000);
     INSN(swap,      4840, fff8, CF_ISA_A);