| Message ID | 8160630afe352f99ec1bba7f64c7cec20268ba64.1431909583.git.alistair.francis@xilinx.com |
|---|---|
| State | New |
| Headers | show |
On Mon, May 18, 2015 at 4:14 PM, Alistair Francis <alistair.francis@xilinx.com> wrote: > Originally the use-fpu PVR bits were manually set for each machine. This > is a hassle and difficult to read, instead set them based on the CPU > properties. > > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> > --- > Changes since RFC: > - Tidy up the if logic > > hw/microblaze/petalogix_ml605_mmu.c | 4 ++-- > target-microblaze/cpu-qom.h | 1 + > target-microblaze/cpu.c | 9 ++++++--- > target-microblaze/translate.c | 6 +++--- > 4 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c > index 48c264b..a93ca51 100644 > --- a/hw/microblaze/petalogix_ml605_mmu.c > +++ b/hw/microblaze/petalogix_ml605_mmu.c > @@ -71,9 +71,8 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu) > env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ > /* setup pvr to match kernel setting */ > env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; > - env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI; > + env->pvr.regs[0] |= PVR0_ENDI; > env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8); > - env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK; > env->pvr.regs[4] = 0xc56b8000; > env->pvr.regs[5] = 0xc56be000; > } > @@ -95,6 +94,7 @@ petalogix_ml605_init(MachineState *machine) > > /* init CPUs */ > cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); > + object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort); > object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); > > /* Attach emulated BRAM through the LMB. */ > diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h > index 750ff3b..f3312f8 100644 > --- a/target-microblaze/cpu-qom.h > +++ b/target-microblaze/cpu-qom.h > @@ -63,6 +63,7 @@ typedef struct MicroBlazeCPU { > struct { > bool stackproc; > uint32_t base_vectors; > + uint8_t usefpu; > } cfg; > > CPUMBState env; > diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c > index c7ad5d5..ce40a3f 100644 > --- a/target-microblaze/cpu.c > +++ b/target-microblaze/cpu.c > @@ -113,12 +113,14 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > | PVR2_USE_DIV_MASK \ > | PVR2_USE_HW_MUL_MASK \ > | PVR2_USE_MUL64_MASK \ > - | PVR2_USE_FPU_MASK \ > - | PVR2_USE_FPU2_MASK \ > | PVR2_FPU_EXC_MASK \ > | 0; > > - env->pvr.regs[0] |= (cpu->cfg.stackproc ? PVR0_SPROT_MASK : 0); > + env->pvr.regs[0] |= (cpu->cfg.stackproc ? PVR0_SPROT_MASK : 0) | > + (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0); > + > + env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) | > + (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0); > > env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ > env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); > @@ -164,6 +166,7 @@ static Property mb_properties[] = { > DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), > DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackproc, > true), > + DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c > index 19faf40..7383d4d 100644 > --- a/target-microblaze/translate.c > +++ b/target-microblaze/translate.c > @@ -1415,11 +1415,11 @@ static int dec_check_fpuv2(DisasContext *dc) > > r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK; > r is unused, so I think this and the decl. has to be deleted. Otherwise: Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Regards, Peter > - if (!r && (dc->tb_flags & MSR_EE_FLAG)) { > + if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { > tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); > t_gen_raise_exception(dc, EXCP_HW_EXCP); > } > - return r; > + return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK; > } > > static void dec_fpu(DisasContext *dc) > @@ -1428,7 +1428,7 @@ static void dec_fpu(DisasContext *dc) > > if ((dc->tb_flags & MSR_EE_FLAG) > && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) > - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) { > + && (dc->cpu->cfg.usefpu != 1)) { > tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); > t_gen_raise_exception(dc, EXCP_HW_EXCP); > return; > -- > 1.7.1 > >
On Mon, May 25, 2015 at 2:34 PM, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote: > On Mon, May 18, 2015 at 4:14 PM, Alistair Francis > <alistair.francis@xilinx.com> wrote: >> Originally the use-fpu PVR bits were manually set for each machine. This >> is a hassle and difficult to read, instead set them based on the CPU >> properties. >> >> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> >> --- >> Changes since RFC: >> - Tidy up the if logic >> >> hw/microblaze/petalogix_ml605_mmu.c | 4 ++-- >> target-microblaze/cpu-qom.h | 1 + >> target-microblaze/cpu.c | 9 ++++++--- >> target-microblaze/translate.c | 6 +++--- >> 4 files changed, 12 insertions(+), 8 deletions(-) >> >> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c >> index 48c264b..a93ca51 100644 >> --- a/hw/microblaze/petalogix_ml605_mmu.c >> +++ b/hw/microblaze/petalogix_ml605_mmu.c >> @@ -71,9 +71,8 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu) >> env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ >> /* setup pvr to match kernel setting */ >> env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; >> - env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI; >> + env->pvr.regs[0] |= PVR0_ENDI; >> env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8); >> - env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK; >> env->pvr.regs[4] = 0xc56b8000; >> env->pvr.regs[5] = 0xc56be000; >> } >> @@ -95,6 +94,7 @@ petalogix_ml605_init(MachineState *machine) >> >> /* init CPUs */ >> cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); >> + object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort); >> object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); >> >> /* Attach emulated BRAM through the LMB. */ >> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h >> index 750ff3b..f3312f8 100644 >> --- a/target-microblaze/cpu-qom.h >> +++ b/target-microblaze/cpu-qom.h >> @@ -63,6 +63,7 @@ typedef struct MicroBlazeCPU { >> struct { >> bool stackproc; >> uint32_t base_vectors; >> + uint8_t usefpu; >> } cfg; >> >> CPUMBState env; >> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c >> index c7ad5d5..ce40a3f 100644 >> --- a/target-microblaze/cpu.c >> +++ b/target-microblaze/cpu.c >> @@ -113,12 +113,14 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) >> | PVR2_USE_DIV_MASK \ >> | PVR2_USE_HW_MUL_MASK \ >> | PVR2_USE_MUL64_MASK \ >> - | PVR2_USE_FPU_MASK \ >> - | PVR2_USE_FPU2_MASK \ >> | PVR2_FPU_EXC_MASK \ >> | 0; >> >> - env->pvr.regs[0] |= (cpu->cfg.stackproc ? PVR0_SPROT_MASK : 0); >> + env->pvr.regs[0] |= (cpu->cfg.stackproc ? PVR0_SPROT_MASK : 0) | >> + (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0); >> + >> + env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) | >> + (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0); >> >> env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ >> env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); >> @@ -164,6 +166,7 @@ static Property mb_properties[] = { >> DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), >> DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackproc, >> true), >> + DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2), >> DEFINE_PROP_END_OF_LIST(), >> }; >> >> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c >> index 19faf40..7383d4d 100644 >> --- a/target-microblaze/translate.c >> +++ b/target-microblaze/translate.c >> @@ -1415,11 +1415,11 @@ static int dec_check_fpuv2(DisasContext *dc) >> >> r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK; >> > > r is unused, so I think this and the decl. has to be deleted. Good catch, I completely missed that. > > Otherwise: > > Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Thanks Alistair > > Regards, > Peter > >> - if (!r && (dc->tb_flags & MSR_EE_FLAG)) { >> + if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { >> tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); >> t_gen_raise_exception(dc, EXCP_HW_EXCP); >> } >> - return r; >> + return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK; >> } >> >> static void dec_fpu(DisasContext *dc) >> @@ -1428,7 +1428,7 @@ static void dec_fpu(DisasContext *dc) >> >> if ((dc->tb_flags & MSR_EE_FLAG) >> && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) >> - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) { >> + && (dc->cpu->cfg.usefpu != 1)) { >> tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); >> t_gen_raise_exception(dc, EXCP_HW_EXCP); >> return; >> -- >> 1.7.1 >> >> >
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 48c264b..a93ca51 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -71,9 +71,8 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu) env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ /* setup pvr to match kernel setting */ env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; - env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI; + env->pvr.regs[0] |= PVR0_ENDI; env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8); - env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK; env->pvr.regs[4] = 0xc56b8000; env->pvr.regs[5] = 0xc56be000; } @@ -95,6 +94,7 @@ petalogix_ml605_init(MachineState *machine) /* init CPUs */ cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); + object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort); object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); /* Attach emulated BRAM through the LMB. */ diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index 750ff3b..f3312f8 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -63,6 +63,7 @@ typedef struct MicroBlazeCPU { struct { bool stackproc; uint32_t base_vectors; + uint8_t usefpu; } cfg; CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index c7ad5d5..ce40a3f 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -113,12 +113,14 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_USE_DIV_MASK \ | PVR2_USE_HW_MUL_MASK \ | PVR2_USE_MUL64_MASK \ - | PVR2_USE_FPU_MASK \ - | PVR2_USE_FPU2_MASK \ | PVR2_FPU_EXC_MASK \ | 0; - env->pvr.regs[0] |= (cpu->cfg.stackproc ? PVR0_SPROT_MASK : 0); + env->pvr.regs[0] |= (cpu->cfg.stackproc ? PVR0_SPROT_MASK : 0) | + (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0); + + env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) | + (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0); env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); @@ -164,6 +166,7 @@ static Property mb_properties[] = { DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackproc, true), + DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 19faf40..7383d4d 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1415,11 +1415,11 @@ static int dec_check_fpuv2(DisasContext *dc) r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK; - if (!r && (dc->tb_flags & MSR_EE_FLAG)) { + if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } - return r; + return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK; } static void dec_fpu(DisasContext *dc) @@ -1428,7 +1428,7 @@ static void dec_fpu(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) { + && (dc->cpu->cfg.usefpu != 1)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return;
Originally the use-fpu PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> --- Changes since RFC: - Tidy up the if logic hw/microblaze/petalogix_ml605_mmu.c | 4 ++-- target-microblaze/cpu-qom.h | 1 + target-microblaze/cpu.c | 9 ++++++--- target-microblaze/translate.c | 6 +++--- 4 files changed, 12 insertions(+), 8 deletions(-)