| Message ID | 1430926687-25875-2-git-send-email-a.rigo@virtualopensystems.com |
|---|---|
| State | New |
| Headers | show |
On 05/06/2015 08:38 AM, Alvise Rigo wrote: > The purpose of this new bitmap is to flag the memory pages that are in > the middle of LL/SC operations (after a LL, before a SC). > For all these pages, the corresponding TLB entries will be generated > in such a way to force the slow-path. > > The accessors to this bitmap are currently not atomic, but they have to > be so in a real multi-threading TCG. > > Suggested-by: Jani Kokkonen <jani.kokkonen@huawei.com> > Suggested-by: Claudio Fontana <claudio.fontana@huawei.com> > Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> > --- > include/exec/cpu-defs.h | 2 ++ > include/exec/memory.h | 3 ++- > include/exec/ram_addr.h | 19 ++++++++++++++++++- > 3 files changed, 22 insertions(+), 2 deletions(-) > > diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h > index 0ca6f0b..d12cb4c 100644 > --- a/include/exec/cpu-defs.h > +++ b/include/exec/cpu-defs.h > @@ -123,5 +123,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); > #define CPU_COMMON \ > /* soft mmu support */ \ > CPU_COMMON_TLB \ > + /* true if in the middle of a LoadLink/StoreConditional */ \ > + bool ll_sc_context; \ Belongs to a different patch? r~
On Thu, May 7, 2015 at 7:12 PM, Richard Henderson <rth@twiddle.net> wrote: > On 05/06/2015 08:38 AM, Alvise Rigo wrote: >> The purpose of this new bitmap is to flag the memory pages that are in >> the middle of LL/SC operations (after a LL, before a SC). >> For all these pages, the corresponding TLB entries will be generated >> in such a way to force the slow-path. >> >> The accessors to this bitmap are currently not atomic, but they have to >> be so in a real multi-threading TCG. >> >> Suggested-by: Jani Kokkonen <jani.kokkonen@huawei.com> >> Suggested-by: Claudio Fontana <claudio.fontana@huawei.com> >> Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> >> --- >> include/exec/cpu-defs.h | 2 ++ >> include/exec/memory.h | 3 ++- >> include/exec/ram_addr.h | 19 ++++++++++++++++++- >> 3 files changed, 22 insertions(+), 2 deletions(-) >> >> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h >> index 0ca6f0b..d12cb4c 100644 >> --- a/include/exec/cpu-defs.h >> +++ b/include/exec/cpu-defs.h >> @@ -123,5 +123,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); >> #define CPU_COMMON \ >> /* soft mmu support */ \ >> CPU_COMMON_TLB \ >> + /* true if in the middle of a LoadLink/StoreConditional */ \ >> + bool ll_sc_context; \ > > Belongs to a different patch? Yes, it shouldn't be here. Thank you, alvise > > > r~
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 0ca6f0b..d12cb4c 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -123,5 +123,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); #define CPU_COMMON \ /* soft mmu support */ \ CPU_COMMON_TLB \ + /* true if in the middle of a LoadLink/StoreConditional */ \ + bool ll_sc_context; \ #endif diff --git a/include/exec/memory.h b/include/exec/memory.h index 06ffa1d..aadd2cc 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -19,7 +19,8 @@ #define DIRTY_MEMORY_VGA 0 #define DIRTY_MEMORY_CODE 1 #define DIRTY_MEMORY_MIGRATION 2 -#define DIRTY_MEMORY_NUM 3 /* num of dirty bits */ +#define DIRTY_MEMORY_EXCLUSIVE 3 +#define DIRTY_MEMORY_NUM 4 /* num of dirty bits */ #include <stdint.h> #include <stdbool.h> diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index ff558a4..7a448ea 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -21,6 +21,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/xen/xen.h" +#include "qemu/bitmap.h" ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, bool share, const char *mem_path, @@ -199,9 +200,25 @@ static inline void cpu_physical_memory_clear_dirty_range(ram_addr_t start, cpu_physical_memory_clear_dirty_range_type(start, length, DIRTY_MEMORY_CODE); } - void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t length, unsigned client); +static inline void cpu_physical_memory_set_excl_dirty(ram_addr_t addr) +{ + clear_bit(addr >> TARGET_PAGE_BITS, + ram_list.dirty_memory[DIRTY_MEMORY_EXCLUSIVE]); +} + +static inline int cpu_physical_memory_excl_is_dirty(ram_addr_t addr) +{ + return !test_bit(addr >> TARGET_PAGE_BITS, + ram_list.dirty_memory[DIRTY_MEMORY_EXCLUSIVE]); +} + +static inline void cpu_physical_memory_clear_excl_dirty(ram_addr_t addr) +{ + set_bit(addr >> TARGET_PAGE_BITS, + ram_list.dirty_memory[DIRTY_MEMORY_EXCLUSIVE]); +} #endif #endif
The purpose of this new bitmap is to flag the memory pages that are in the middle of LL/SC operations (after a LL, before a SC). For all these pages, the corresponding TLB entries will be generated in such a way to force the slow-path. The accessors to this bitmap are currently not atomic, but they have to be so in a real multi-threading TCG. Suggested-by: Jani Kokkonen <jani.kokkonen@huawei.com> Suggested-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> --- include/exec/cpu-defs.h | 2 ++ include/exec/memory.h | 3 ++- include/exec/ram_addr.h | 19 ++++++++++++++++++- 3 files changed, 22 insertions(+), 2 deletions(-)