From patchwork Fri Mar 22 00:05:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 1060611 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KpWFNwdV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44QP6r4Vyqz9sS0 for ; Fri, 22 Mar 2019 11:05:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727329AbfCVAFH (ORCPT ); Thu, 21 Mar 2019 20:05:07 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:35669 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726460AbfCVAFH (ORCPT ); Thu, 21 Mar 2019 20:05:07 -0400 Received: by mail-wr1-f68.google.com with SMTP id w1so471207wrp.2; Thu, 21 Mar 2019 17:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=XD/iehXQ9b1kkwV+/SVBtjtusUz3OHDFJBHrIgNYHq8=; b=KpWFNwdVySbvGOdwx589b8inb/JMsoherXI1l0fW2ikfOXTg+c73y9m939douCku+h 2ZeE3KpJWth5q/t//dB+aNcaxDRcPq2chtxZBu9bHeZ26uCuHf7PIEjZA8z29PgbZxqQ cwQpEUbNdQe/Kx6nREz5Sp1N4n4vUTHGyO81mFBFmjMSJwaP+ACPqbK3MpQhxnBshEQm Z2LcC2nOOBE1KhW9hzdnbDspPMVBhYAyL4670Ae6l03gQwnrJY6VDu+zQnfTTUMhYRXE CEK2IzDNCKCdrXdEGNDwdcjcWc9GConSMsefFoKOe6GtAyn1jVN7JYkBFJAYUQS57spt MU1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=XD/iehXQ9b1kkwV+/SVBtjtusUz3OHDFJBHrIgNYHq8=; b=AxGVDIn2QStSxhrhmVZg1oQxWRinNh+FsFwJKr+5EOQDWpLSb3hOVaRA53uXmaLA3R C9kAvlq+0wNJDLZvW7hui6Xscc1PYhAOUCg0B83b0seMBb0PJ8AMP3K17SZ/C2DMTzF8 BSc3XhP6rgzeNgT8fDGT0WqrQBFzBTH/wApxTjOGH8FHYc63qhjr03e3dYyUZSUMCMWa Gz5QVOh3gDQmPkvP+2gpT7DAI0I1dYHtwJtawWKOgeoqHFIDs8qPi2nNJ6N1JQhMljiV XVEUk9GlRnMYEreqwyXsLy8KRmOtuXRJAqJKJgsO2p+hptugMmiXfP+Ajo/m94cOcpcP XucA== X-Gm-Message-State: APjAAAXxYI33rmRe+0Y3IhY19x6No9hzuklwjpTqpu7BS3CMiM6Khjvt ScHa+aRV/c3+Jz/T2F01nUmmU5TI X-Google-Smtp-Source: APXvYqzyLegmdi0UfrA1WqIQaDduVOV1xwuc31p32OvX6gT0+K6mhgBxdgRWdvojBOThpH8SeWtS5A== X-Received: by 2002:adf:e889:: with SMTP id d9mr4518247wrm.162.1553213104796; Thu, 21 Mar 2019 17:05:04 -0700 (PDT) Received: from debian64.daheim (p4FD091E7.dip0.t-ipconnect.de. [79.208.145.231]) by smtp.gmail.com with ESMTPSA id o15sm2450153wrj.59.2019.03.21.17.05.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Mar 2019 17:05:04 -0700 (PDT) Received: from chuck by debian64.daheim with local (Exim 4.92) (envelope-from ) id 1h77gF-0005qX-LS; Fri, 22 Mar 2019 01:05:03 +0100 From: Christian Lamparter To: netdev@vger.kernel.org, devicetree@vger.kernel.org Cc: Florian Fainelli , Vivien Didelot , Andrew Lunn , Rob Herring , Mark Rutland , Marek Behun Subject: [PATCH v4 1/4] dt-bindings: net: dsa: qca8k: fix example Date: Fri, 22 Mar 2019 01:05:00 +0100 Message-Id: <20190322000503.22431-1-chunkeey@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org In the example, the phy at phy@0 is clashing with the switch0@0 at the same address. Usually, the switches are accessible through pseudo PHYs which in case of the qca8k are located at 0x10 - 0x18. Reviewed-by: Florian Fainelli Signed-off-by: Christian Lamparter --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index bbcb255c3150..5eda99e6c86e 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -55,12 +55,12 @@ Example: reg = <4>; }; - switch0@0 { + switch@10 { compatible = "qca,qca8337"; #address-cells = <1>; #size-cells = <0>; - reg = <0>; + reg = <0x10>; ports { #address-cells = <1>; From patchwork Fri Mar 22 00:05:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 1060612 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="o9pPH7gG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44QP6s3DzKz9sS1 for ; Fri, 22 Mar 2019 11:05:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727366AbfCVAFI (ORCPT ); Thu, 21 Mar 2019 20:05:08 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:32935 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727162AbfCVAFH (ORCPT ); Thu, 21 Mar 2019 20:05:07 -0400 Received: by mail-wr1-f65.google.com with SMTP id q1so480832wrp.0; Thu, 21 Mar 2019 17:05:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2/5WbOb3mxa6P+a5dhjeVwMTha1NiVZwCLDCjO2L1Ds=; b=o9pPH7gGj2kahyMWF3nl3yq/Y9V+mjzXEL7d3FTMnsYYt47qYaq1zY0nLdZhWWyur5 PAY+LvK+nM6erDCYQTWOVfbZzGRuabwT8FrO4wZ0/amvQ7Y4GEL+FXKojbCevfiCZjJ1 lBqylwBG+slEsxQiX59Yhoc2Ay9yud0iUg0w/EVDX5im2jGHE2Krhf00O5W267IfnLze ZqJR1kp9P/aK+zLFR6BjgcYHt7psyNB2DBBxdCNu8sLMv3S9K7sFJNaypUOdurVzqA2Y iwyZ24HBK79/op5VajM2BXaHf/cOoeFH0vdiDCD2Hzqy+5Nzr8TZt3lovxDFk8g01ApA 6iQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2/5WbOb3mxa6P+a5dhjeVwMTha1NiVZwCLDCjO2L1Ds=; b=TT2ZSgnkb9zszDqKTNn0gh4gaj+o/Rm43sCcIp5kRiD34H92FyO+q9HECAFpoGknde aM9FtagrtIsM38KFnSz1CQ8WvGwPM+ERV60FtcBrVM2/DTZ4YPkWVYaMfAqnvUaN2zaj mKM21BQArUpOWK3M0auwmfljzuo7/Noyr0pgJAtjwR/3pT3YrtujAe7kkVxqiv/NenAt t/WE0uvQEQhzgUC0VlXI+uvY0GxfGHCIv2RUHxrnDtRaa7GhOoJdAZ5qe0LBQJUwHc4q FDgc0Zaef9M9yts3LbT9HRtren1IQgrvfQNbQpOWYVV1Fv6OCEGYxEHVJ3VnMr8UG0UW rXDQ== X-Gm-Message-State: APjAAAVF2W0bgKeqfTnoHagX43jIDwWwxBJdhJ8I9KPRI8d39E4g30+B yxyS4HsNJGAduoO1bPczQ2x1b450 X-Google-Smtp-Source: APXvYqz0cNnKxIwjoY+1bIUPZQPOhSpLb+GYJnHCA5ogwOdKg6/jRB8Ww+q9haiycjG2eMsbSQjSKg== X-Received: by 2002:a05:6000:10c9:: with SMTP id b9mr4170637wrx.281.1553213105153; Thu, 21 Mar 2019 17:05:05 -0700 (PDT) Received: from debian64.daheim (p4FD091E7.dip0.t-ipconnect.de. [79.208.145.231]) by smtp.gmail.com with ESMTPSA id z19sm1234328wml.44.2019.03.21.17.05.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Mar 2019 17:05:04 -0700 (PDT) Received: from chuck by debian64.daheim with local (Exim 4.92) (envelope-from ) id 1h77gF-0005qb-MD; Fri, 22 Mar 2019 01:05:03 +0100 From: Christian Lamparter To: netdev@vger.kernel.org, devicetree@vger.kernel.org Cc: Florian Fainelli , Vivien Didelot , Andrew Lunn , Rob Herring , Mark Rutland , Marek Behun Subject: [PATCH v4 2/4] dt-bindings: net: dsa: qca8k: support internal mdio-bus Date: Fri, 22 Mar 2019 01:05:01 +0100 Message-Id: <20190322000503.22431-2-chunkeey@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190322000503.22431-1-chunkeey@gmail.com> References: <20190322000503.22431-1-chunkeey@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch updates the qca8k's binding to document to the approach for using the internal mdio-bus of the supported qca8k switches. Reviewed-by: Florian Fainelli Signed-off-by: Christian Lamparter --- .../devicetree/bindings/net/dsa/qca8k.txt | 69 +++++++++++++++++-- 1 file changed, 64 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 5eda99e6c86e..93a7469e70d4 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -12,10 +12,15 @@ Required properties: Subnodes: The integrated switch subnode should be specified according to the binding -described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of -port and PHY id, each subnode describing a port needs to have a valid phandle -referencing the internal PHY connected to it. The CPU port of this switch is -always port 0. +described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external +mdio-bus each subnode describing a port needs to have a valid phandle +referencing the internal PHY it is connected to. This is because there's no +N:N mapping of port and PHY id. + +Don't use mixed external and internal mdio-bus configurations, as this is +not supported by the hardware. + +The CPU port of this switch is always port 0. A CPU port node has the following optional node: @@ -31,8 +36,9 @@ For QCA8K the 'fixed-link' sub-node supports only the following properties: - 'full-duplex' (boolean, optional), to indicate that full duplex is used. When absent, half duplex is assumed. -Example: +Examples: +for the external mdio-bus configuration: &mdio0 { phy_port1: phy@0 { @@ -108,3 +114,56 @@ Example: }; }; }; + +for the internal master mdio-bus configuration: + + &mdio0 { + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + fixed-link { + speed = 1000; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "wan"; + }; + }; + }; + }; From patchwork Fri Mar 22 00:05:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 1060613 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UuvAyF5K"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44QP6v4qGJz9sRx for ; Fri, 22 Mar 2019 11:05:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727375AbfCVAFK (ORCPT ); Thu, 21 Mar 2019 20:05:10 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:38251 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727251AbfCVAFI (ORCPT ); Thu, 21 Mar 2019 20:05:08 -0400 Received: by mail-wm1-f68.google.com with SMTP id a188so475389wmf.3; Thu, 21 Mar 2019 17:05:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AWSS4ZeyIqEuO+k/uGTwjoIiMvVkiqyU0VrU837f+Is=; b=UuvAyF5KEo6ZQStVWDK7JiTpDm9zXQiC+vAmLIL62epQW4OlpIOpUycdL2h6nHbcRQ JqGYl1vRk9JL+5FExykxhA0bL+/Hr816HehHselVLB3YuaojyDvqK6D5Zq9tagL84HHT 3hnqHdIBdVQLvCPRZmZ/DkOtMoucDbM3GPHBQQMx+AmBjK0QXtQoI9Uas1V/24eV3cKJ nCM870DD12KJ2tQBu0Dznh+pPiQ3a4Sci76+EjlznvX07zS1IO0jRQDYCj020//DBS7y cxK0ic7Cq6V4wQcPw99cPOBY8yXjMBU1TiitCwaZrbEqFXudp7ir1zHT1/fESXYhDoYM e/8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AWSS4ZeyIqEuO+k/uGTwjoIiMvVkiqyU0VrU837f+Is=; b=j88yO4mJxZXvnGdxR9jLxJ+XDiWc5+xay+s4TNjefADYm71+1eRZpvWVTY16Jf7uk2 cRcBgtopvFwIZP01Etyas5MMW4A6jJqpw7YiB5Qz6gzMHdxQJvODBGH69tGK29U6mCA7 Vd1uWaj4N6i2qH9nyR7BV1/jCfzQ0N+1LH8PJfbMwJ3CmiFv+XBK25HYTM0zZeizuwx7 LswvuS1ZBniCoyheZXVMGDcOMlBz6A20EJh6nJhK2blt3/LsqZq4v0Mf7SAtljPaDWoS 12YLyKpOdroWd/GPb4qjMTjyVf37tNOVeoX472N+l/pGFe3FpxPMbFYDMg2HY24cLaKw xp4w== X-Gm-Message-State: APjAAAVwxTanuJvUc4Fq6IbJiQtPUay0AdaHd8PpRFocNI+nnJyuMVQ1 78zSGRHAl55UPJJzFE9Tb8e1ru1B X-Google-Smtp-Source: APXvYqwgmyBtuX2N+6wBFWq0mELebRAtKfpvDpOF5fgLza7C6iy0F38pAe1Jxj6obe22mX0ZZnqGDg== X-Received: by 2002:a1c:eb17:: with SMTP id j23mr1058805wmh.86.1553213105969; Thu, 21 Mar 2019 17:05:05 -0700 (PDT) Received: from debian64.daheim (p4FD091E7.dip0.t-ipconnect.de. [79.208.145.231]) by smtp.gmail.com with ESMTPSA id w24sm6412376wmi.40.2019.03.21.17.05.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Mar 2019 17:05:04 -0700 (PDT) Received: from chuck by debian64.daheim with local (Exim 4.92) (envelope-from ) id 1h77gF-0005qg-NM; Fri, 22 Mar 2019 01:05:03 +0100 From: Christian Lamparter To: netdev@vger.kernel.org, devicetree@vger.kernel.org Cc: Florian Fainelli , Vivien Didelot , Andrew Lunn , Rob Herring , Mark Rutland , Marek Behun Subject: [PATCH v4 3/4] net: dsa: qca8k: remove leftover phy accessors Date: Fri, 22 Mar 2019 01:05:02 +0100 Message-Id: <20190322000503.22431-3-chunkeey@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190322000503.22431-1-chunkeey@gmail.com> References: <20190322000503.22431-1-chunkeey@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This belated patch implements Andrew Lunn's request of "remove the phy_read() and phy_write() functions." While seemingly harmless, this causes the switch's user port PHYs to get registered twice. This is because the DSA subsystem will create a slave mdio-bus not knowing that the qca8k_phy_(read|write) accessors operate on the external mdio-bus. So the same "bus" gets effectively duplicated. Cc: stable@vger.kernel.org Fixes: 6b93fb46480a ("net-next: dsa: add new driver for qca8xxx family") Signed-off-by: Christian Lamparter --- This (standalone) patch should be much easier to backport than the big one. --- drivers/net/dsa/qca8k.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 576b37d12a63..14ad78225f07 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -624,22 +624,6 @@ qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy) qca8k_port_set_status(priv, port, 1); } -static int -qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - - return mdiobus_read(priv->bus, phy, regnum); -} - -static int -qca8k_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - - return mdiobus_write(priv->bus, phy, regnum, val); -} - static void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data) { @@ -879,8 +863,6 @@ static const struct dsa_switch_ops qca8k_switch_ops = { .setup = qca8k_setup, .adjust_link = qca8k_adjust_link, .get_strings = qca8k_get_strings, - .phy_read = qca8k_phy_read, - .phy_write = qca8k_phy_write, .get_ethtool_stats = qca8k_get_ethtool_stats, .get_sset_count = qca8k_get_sset_count, .get_mac_eee = qca8k_get_mac_eee, From patchwork Fri Mar 22 00:05:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 1060614 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hDmK81ru"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44QP6y3L16z9sRy for ; Fri, 22 Mar 2019 11:05:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727385AbfCVAFN (ORCPT ); Thu, 21 Mar 2019 20:05:13 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:45035 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727283AbfCVAFJ (ORCPT ); Thu, 21 Mar 2019 20:05:09 -0400 Received: by mail-wr1-f66.google.com with SMTP id w2so423262wrt.11; Thu, 21 Mar 2019 17:05:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EGghVqOUOFlCRlrorU680LltieX/gwE0+ytqQkIDqbk=; b=hDmK81ruV48FG5Hcmeh1HIc9dZ0Y8gPEChBPGAyMJjJ//Se7qdBGJZb6NI2y+ejn7+ DtTXceXB4/53j7RZI034FzXSBKsbp2YaEbUPHForjUNYysj3Wvf0fKnLsXb3WTHUlP3H lz23CCy5pn7hTInA1mMq9seW6IO8zbQOTeJgZfOj8n5p3W1BCx4wHap0WHIKct+ApPAg /7JFpPQ4/qqti5WbrukN8Cw0jTGNdyt554b8V6jcX0brkfKpFO9YOowk1HJLlqo/uuNc WxdIGIGVBAzy7idQoBThmmEd5gRKKHeY+PjAi+ooUU/YJ67H0sUAeTcBnPdW9sG1ixEK hEiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EGghVqOUOFlCRlrorU680LltieX/gwE0+ytqQkIDqbk=; b=d45LFRldFkmAsO++hcaUNUd7DwLwNESd9dBZW4oC5yC+nvfLkKt7xvttp33BEdBWlv W5dLMegwp9UktSoKYC+1f675X0GvmQIqVlgwe4B82NcYcyqB8mrZ1bRMDsdDuP1Bt6Vi NBUpCTbXdzRdtrqFZc5Dd2bR12ylTjFGCjTV8j3ffD8WBjxBSZkNpItizHY59wImhhyY k3NgORAFtB5eJ+cpPedxTG7i6rBB+2mmlbp9gdDxZcMtWKDVpzL17oGOq6lZjdTMcdG+ 3DL8q0S66cJxDwv/AepkZ3h+oRehQnq4Fj9+xS4sQ7YVaP7UiKyEAe1jaoyTjL1Tymvn 8ULA== X-Gm-Message-State: APjAAAXksmHIQN3n7/plcjFAiVcvJj841J1lHa7wbx0yaNd3mc3ScICi LXEnrWEGXBuj49ONmAyjPbZ3+upo X-Google-Smtp-Source: APXvYqzIfx/ZUqmYqL10sKe6YOCeaM8/BXf4v2llBcyd/Az7gZ0WaY2kEQX2cCqONBdZGxS3fkL7qA== X-Received: by 2002:adf:dd8c:: with SMTP id x12mr4522798wrl.262.1553213106417; Thu, 21 Mar 2019 17:05:06 -0700 (PDT) Received: from debian64.daheim (p4FD091E7.dip0.t-ipconnect.de. [79.208.145.231]) by smtp.gmail.com with ESMTPSA id v20sm13165935wmj.2.2019.03.21.17.05.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Mar 2019 17:05:04 -0700 (PDT) Received: from chuck by debian64.daheim with local (Exim 4.92) (envelope-from ) id 1h77gF-0005qk-O6; Fri, 22 Mar 2019 01:05:03 +0100 From: Christian Lamparter To: netdev@vger.kernel.org, devicetree@vger.kernel.org Cc: Florian Fainelli , Vivien Didelot , Andrew Lunn , Rob Herring , Mark Rutland , Marek Behun Subject: [PATCH v4 4/4] net: dsa: qca8k: extend slave-bus implementations Date: Fri, 22 Mar 2019 01:05:03 +0100 Message-Id: <20190322000503.22431-4-chunkeey@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190322000503.22431-1-chunkeey@gmail.com> References: <20190322000503.22431-1-chunkeey@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch implements accessors for the QCA8337 MDIO access through the MDIO_MASTER register, which makes it possible to access the PHYs on slave-bus through the switch. In cases where the switch ports are already mapped via external "phy-phandles", the internal mdio-bus is disabled in order to prevent a duplicated discovery and enumeration of the same PHYs. Don't use mixed external and internal mdio-bus configurations, as this is not supported by the hardware. Signed-off-by: Christian Lamparter --- Changes from v3: - removed unneccessary PHYAD checks - let dsa subsystem setup the slave bus, but only if needed - saved an indent level in qca8k_setup_mdio_bus() - Reverse XMAS tree-ized Changes from v2: - Make it compatible with existing configurations - make it clear that's sadly a either external or internal mdio bus access. Changes from v1: - drop DT port <-> phy mapping - added register definitions for the MDIO control register - implemented new slave-mdio bus accessors - DT-binding: fix switch's PSEUDO_PHY address. It's 0x10 not 0. Old patch (+ discussion) for reference: Tested on a Compex WPQ864 (IPQ8064 + QCA8337N) internal bus: qca8k 37000000.mdio-mii:10 lan1 (uninitialized): PHY [dsa-0.0:01] driver [Generic PHY] qca8k 37000000.mdio-mii:10 lan2 (uninitialized): PHY [dsa-0.0:02] driver [Generic PHY] qca8k 37000000.mdio-mii:10 lan3 (uninitialized): PHY [dsa-0.0:03] driver [Generic PHY] qca8k 37000000.mdio-mii:10 lan4 (uninitialized): PHY [dsa-0.0:04] driver [Generic PHY] qca8k 37000000.mdio-mii:10 wan (uninitialized): PHY [dsa-0.0:05] driver [Generic PHY] external bus: qca8k 37000000.mdio-mii:10 lan1 (uninitialized): PHY [37000000.mdio-mii:00] driver [Generic PHY] qca8k 37000000.mdio-mii:10 lan2 (uninitialized): PHY [37000000.mdio-mii:01] driver [Generic PHY] qca8k 37000000.mdio-mii:10 lan3 (uninitialized): PHY [37000000.mdio-mii:02] driver [Generic PHY] qca8k 37000000.mdio-mii:10 lan4 (uninitialized): PHY [37000000.mdio-mii:03] driver [Generic PHY] qca8k 37000000.mdio-mii:10 wan (uninitialized): PHY [37000000.mdio-mii:04] driver [Generic PHY] --- drivers/net/dsa/qca8k.c | 156 +++++++++++++++++++++++++++++++++++++++- drivers/net/dsa/qca8k.h | 13 ++++ 2 files changed, 168 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 14ad78225f07..c4fa400efdcc 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -481,6 +481,155 @@ qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable) qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask); } +static u32 +qca8k_port_to_phy(int port) +{ + /* From Andrew Lunn: + * Port 0 has no internal phy. + * Port 1 has an internal PHY at MDIO address 0. + * Port 2 has an internal PHY at MDIO address 1. + * ... + * Port 5 has an internal PHY at MDIO address 4. + * Port 6 has no internal PHY. + */ + + return port - 1; +} + +static int +qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) +{ + u32 phy, val; + + if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) + return -EINVAL; + + /* callee is responsible for not passing bad ports, + * but we still would like to make spills impossible. + */ + phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; + val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | + QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | + QCA8K_MDIO_MASTER_REG_ADDR(regnum) | + QCA8K_MDIO_MASTER_DATA(data); + + qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + + return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); +} + +static int +qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) +{ + u32 phy, val; + + if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) + return -EINVAL; + + /* callee is responsible for not passing bad ports, + * but we still would like to make spills impossible. + */ + phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; + val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | + QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | + QCA8K_MDIO_MASTER_REG_ADDR(regnum); + + qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + + if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY)) + return -ETIMEDOUT; + + val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & + QCA8K_MDIO_MASTER_DATA_MASK); + + return val; +} + +static int +qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data) +{ + struct qca8k_priv *priv = ds->priv; + + return qca8k_mdio_write(priv, port, regnum, data); +} + +static int +qca8k_phy_read(struct dsa_switch *ds, int port, int regnum) +{ + struct qca8k_priv *priv = ds->priv; + int ret; + + ret = qca8k_mdio_read(priv, port, regnum); + + if (ret < 0) + return 0xffff; + + return ret; +} + +static int +qca8k_setup_mdio_bus(struct qca8k_priv *priv) +{ + u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg; + struct device_node *ports, *port; + int err; + + ports = of_get_child_by_name(priv->dev->of_node, "ports"); + if (!ports) + return -EINVAL; + + for_each_available_child_of_node(ports, port) { + err = of_property_read_u32(port, "reg", ®); + if (err) + return err; + + if (!dsa_is_user_port(priv->ds, reg)) + continue; + + if (of_property_read_bool(port, "phy-handle")) + external_mdio_mask |= BIT(reg); + else + internal_mdio_mask |= BIT(reg); + } + + if (!external_mdio_mask && !internal_mdio_mask) { + dev_err(priv->dev, "no PHYs are defined.\n"); + return -EINVAL; + } + + /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through + * the MDIO_MASTER register also _disconnects_ the external MDC + * passthrough to the internal PHYs. It's not possible to use both + * configurations at the same time! + * + * Because this came up during the review process: + * If the external mdio-bus driver is capable magically disabling + * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's + * accessors for the time being, it would be possible to pull this + * off. + */ + if (!!external_mdio_mask && !!internal_mdio_mask) { + dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n"); + return -EINVAL; + } + + if (external_mdio_mask) { + /* Make sure to disable the internal mdio bus in cases + * a dt-overlay and driver reload changed the configuration + */ + + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + return 0; + } + + priv->ops.phy_read = qca8k_phy_read; + priv->ops.phy_write = qca8k_phy_write; + return 0; +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -502,6 +651,10 @@ qca8k_setup(struct dsa_switch *ds) if (IS_ERR(priv->regmap)) pr_warn("regmap initialization failed"); + ret = qca8k_setup_mdio_bus(priv); + if (ret) + return ret; + /* Initialize CPU port pad mode (xMII type, delays...) */ phy_mode = of_get_phy_mode(ds->ports[QCA8K_CPU_PORT].dn); if (phy_mode < 0) { @@ -905,7 +1058,8 @@ qca8k_sw_probe(struct mdio_device *mdiodev) return -ENOMEM; priv->ds->priv = priv; - priv->ds->ops = &qca8k_switch_ops; + priv->ops = qca8k_switch_ops; + priv->ds->ops = &priv->ops; mutex_init(&priv->reg_mutex); dev_set_drvdata(&mdiodev->dev, priv); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index d146e54c8a6c..249fd62268e5 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -49,6 +49,18 @@ #define QCA8K_MIB_FLUSH BIT(24) #define QCA8K_MIB_CPU_KEEP BIT(20) #define QCA8K_MIB_BUSY BIT(17) +#define QCA8K_MDIO_MASTER_CTRL 0x3c +#define QCA8K_MDIO_MASTER_BUSY BIT(31) +#define QCA8K_MDIO_MASTER_EN BIT(30) +#define QCA8K_MDIO_MASTER_READ BIT(27) +#define QCA8K_MDIO_MASTER_WRITE 0 +#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26) +#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21) +#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16) +#define QCA8K_MDIO_MASTER_DATA(x) (x) +#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0) +#define QCA8K_MDIO_MASTER_MAX_PORTS 5 +#define QCA8K_MDIO_MASTER_MAX_REG 32 #define QCA8K_GOL_MAC_ADDR0 0x60 #define QCA8K_GOL_MAC_ADDR1 0x64 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) @@ -169,6 +181,7 @@ struct qca8k_priv { struct dsa_switch *ds; struct mutex reg_mutex; struct device *dev; + struct dsa_switch_ops ops; }; struct qca8k_mib_desc {