From patchwork Thu Mar 21 17:17:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1060307 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="AcCv+oJI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44QD6J5Bjvz9s6w for ; Fri, 22 Mar 2019 04:19:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728729AbfCURSQ (ORCPT ); Thu, 21 Mar 2019 13:18:16 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:40794 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728728AbfCURSP (ORCPT ); Thu, 21 Mar 2019 13:18:15 -0400 Received: by mail-pg1-f196.google.com with SMTP id u9so4631208pgo.7 for ; Thu, 21 Mar 2019 10:18:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o+6vk1Y2CFYMkd90yT6sdZwK6wtMV3xm69BtCbUlzG0=; b=AcCv+oJIKvG54X4XIiKChRRBCd64AapLB03O1VpSotZHO9pkVYNgVtpiqQj2758g9m /bbeXL+FYzwfrqgV56tZjw8rHbWq6/la1mXbKA6fgDz0A2HkIG5ZN+nNlvUEHbXVo4xn 7AnHRKXYM+VFZqQ6SCItRG5ArIKdREVkGNUoc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o+6vk1Y2CFYMkd90yT6sdZwK6wtMV3xm69BtCbUlzG0=; b=SMdszzCRueIV8i5XMO/VAa/LSF9pTsLrEJ/3Fitx1/jTIVYvlWypcD7BOObnTborA6 khrr2UazvkcMYb9crBp6CaISvahhg3tW4hQw+mm50u08SDdaz7waxhEr6oPnLSEEDO7c OLHhQXxeWc9l6fbmeznZGThC6KH2T3/iLKJPftsWoshf0zsK7uuAqCdJlyLQ/5WrlWmP AAAMBB294K613P6rv8MfNgaEQN2Z9J7qmYnPao+MvRl/RA4poioWi2cdtnQhY8AIx2qv ZTMh95IikRjX2gDNVFo40GtCGgfDo07Pc7Aoeccyry1k/Rkbg9HV9Ami+oBeRGG0usWD eNxw== X-Gm-Message-State: APjAAAWxkjV0MJfJcdzBP0VTr2xz4pGJKp9wXM6lJG6kWcR92+yoBGQw 9ilJlaLEG5kxFn5fsPtjA6wWXA== X-Google-Smtp-Source: APXvYqwZ7A3/SO3Qyiz1HQnNKa9WPyj7Ebk6Ogmp2TQl43qx6oz1cGdoAJ6LzNGvQPj7G7ny3uHZ5A== X-Received: by 2002:a17:902:8692:: with SMTP id g18mr4519908plo.149.1553188694579; Thu, 21 Mar 2019 10:18:14 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id z6sm20953866pgo.31.2019.03.21.10.18.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Mar 2019 10:18:13 -0700 (PDT) From: Evan Green To: Kishon Vijay Abraham I Cc: Stephen Boyd , Marc Gonzalez , Can Guo , Vivek Gautam , Douglas Anderson , Asutosh Das , Evan Green , Rob Herring , devicetree@vger.kernel.org, liwei , linux-kernel@vger.kernel.org, Subhash Jadavani , "Martin K. Petersen" , Rob Herring , Mark Rutland Subject: [PATCH v5 1/8] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers Date: Thu, 21 Mar 2019 10:17:53 -0700 Message-Id: <20190321171800.104681-2-evgreen@chromium.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190321171800.104681-1-evgreen@chromium.org> References: <20190321171800.104681-1-evgreen@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable Qualcomm UFS controllers to expose the PHY reset via a reset controller. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 5111e9130bc3..f647c09bc62a 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -50,6 +50,8 @@ Optional properties: -lanes-per-direction : number of lanes available per direction - either 1 or 2. Note that it is assume same number of lanes is used both directions at once. If not specified, default is 2 lanes per direction. +- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose + PHY reset from the UFS controller. - resets : reset node register - reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP. @@ -79,4 +81,5 @@ Example: reset-names = "rst"; phys = <&ufsphy1>; phy-names = "ufsphy"; + #reset-cells = <1>; }; From patchwork Thu Mar 21 17:17:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1060306 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Kr1Bi0yt"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44QD6H3W4bz9s6w for ; Fri, 22 Mar 2019 04:19:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728752AbfCURSS (ORCPT ); Thu, 21 Mar 2019 13:18:18 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:33435 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728748AbfCURSS (ORCPT ); Thu, 21 Mar 2019 13:18:18 -0400 Received: by mail-pg1-f194.google.com with SMTP id b12so4666919pgk.0 for ; Thu, 21 Mar 2019 10:18:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5VTcVo1Chs4XGa35tec1xGg2FL/05IcVUKqdSKt+U9Q=; b=Kr1Bi0ytzlIExrHApFqy1i2jPUQf5/OokIJmBfy88t6HmBn28AzgN6842rJUZ2wmQx LCQ0JbLwZpGjnZIYqJaa2e5V2i/f+jtne9UBW62i8YsOzXXWUy91ZxTlU4Em4XNQ2krG Z3n2muBhDqKmlKuIu8zh5BF2z13WJk+9N3Zek= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5VTcVo1Chs4XGa35tec1xGg2FL/05IcVUKqdSKt+U9Q=; b=FexJsYjO2QhM+OWSfKYEQ5pvNbbQLF1zxDcVtkQv2Zx6hjqibzkoik4uBuBwggpqsy +/JBaYtltbQGajq5n7+xUlhTa3sb3MWTqYxe4FBDTLT4wTzAE9hnjUm0jGbGbvGK1SYR Bkq100rNn55o2IBVbJj9OqYN1Y5/0A2uTLWd86RGI7yzsWQ4hM6KRrYbBhq+DYodTt2F AAVagdCOmynZxn2mH1CHBUWh6e+QPYexTMynstrlHX3os/XZjgMe1ymKMA6VqkZhQhm0 h0vFtdnfHcMHhLwI2OtGtvEeRFyouxwAT8vtsBULYofrHkbNVWKIxQThEmMLzb+AE0Y5 I2gQ== X-Gm-Message-State: APjAAAVhB9jx8VCxo62vJ1h5Yvc7qerj7PPwa3TR5bYrRu0hR9Fmndxt XywNVL75mc3SWcTrXVnNa6PQXQ== X-Google-Smtp-Source: APXvYqwVkUQOfEPbsJoytpmNSpCN+m2u6x55lnqBlfVlHlhBkUsE+bGCQubPjDMcBfyYPanRj2vq8A== X-Received: by 2002:a62:a219:: with SMTP id m25mr4396024pff.197.1553188697650; Thu, 21 Mar 2019 10:18:17 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id z6sm20953866pgo.31.2019.03.21.10.18.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Mar 2019 10:18:17 -0700 (PDT) From: Evan Green To: Kishon Vijay Abraham I Cc: Stephen Boyd , Marc Gonzalez , Can Guo , Vivek Gautam , Douglas Anderson , Asutosh Das , Evan Green , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , Mark Rutland , Rob Herring Subject: [PATCH v5 2/8] dt-bindings: phy-qcom-qmp: Add UFS PHY reset Date: Thu, 21 Mar 2019 10:17:54 -0700 Message-Id: <20190321171800.104681-3-evgreen@chromium.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190321171800.104681-1-evgreen@chromium.org> References: <20190321171800.104681-1-evgreen@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a required reset to the SDM845 UFS phy to express the PHY reset bit inside the UFS controller register space. Before this change, this reset was not expressed in the DT, and the driver utilized two different callbacks (phy_init and phy_poweron) to implement a two-phase initialization procedure that involved deasserting this reset between init and poweron. This abused the two callbacks and diluted their purpose. That scheme does not work as regulators cannot be turned off in phy_poweroff because they were turned on in init, rather than poweron. The net result is that regulators are left on in suspend that shouldn't be. This new scheme gives the UFS reset to the PHY, so that it can fully initialize itself in a single callback. We can then turn regulators on during poweron and off during poweroff. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 5d181fc3cc18..4a78ba8b85bc 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -59,7 +59,8 @@ Required properties: one for each entry in reset-names. - reset-names: "phy" for reset of phy block, "common" for phy common block reset, - "cfg" for phy's ahb cfg block reset. + "cfg" for phy's ahb cfg block reset, + "ufsphy" for the PHY reset in the UFS controller. For "qcom,ipq8074-qmp-pcie-phy" must contain: "phy", "common". @@ -74,7 +75,8 @@ Required properties: "phy", "common". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: "phy", "common". - For "qcom,sdm845-qmp-ufs-phy": no resets are listed. + For "qcom,sdm845-qmp-ufs-phy": must contain: + "ufsphy". - vdda-phy-supply: Phandle to a regulator supply to PHY core block. - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. From patchwork Thu Mar 21 17:17:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1060305 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="UndNXci+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44QD6F0xYtz9s6w for ; Fri, 22 Mar 2019 04:19:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728766AbfCURSW (ORCPT ); Thu, 21 Mar 2019 13:18:22 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:42710 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728602AbfCURSV (ORCPT ); Thu, 21 Mar 2019 13:18:21 -0400 Received: by mail-pf1-f194.google.com with SMTP id r15so4705514pfn.9 for ; Thu, 21 Mar 2019 10:18:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Bo6Ts3kPT4RmjlVO3KjUyTjhP8WkrwI/aNrar/qliw=; b=UndNXci+1z/Eg7Aq+ZV0SQHvpe+4Jhdi7/ROwPgizumfm4yMF33jHRwWBZmema9QlX 9sr0tOcPYnJWR42rGspd2OFFHvryg7x2ifOIRvecOH/B53DqA1nTQNfUEhdzSqpStSXB gGe9QJR3GOl3I/1ee8z/v72+lCdq/Af1L3oQQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Bo6Ts3kPT4RmjlVO3KjUyTjhP8WkrwI/aNrar/qliw=; b=Hk1P4E8eaXvnvKFkAATsDItOiTyB95wBg7Q+xYWRgdtFcnAhf4TGRZhT01PSnj21lY B2H2kLokgyq/7evA4tg9fORWAnqj3TD+k45/7I57Fd2Yr0tjzOiHVUi4ukPgxIu7L1e4 0TAm6HI7WS+2dt2xlQf6oT9Wbh5Ecd8FR6W0WkIMcJaRpaeh8KBFEGjnWoY+MGE+CxOS GcS6JLnaD9eit9R3P/PkOIUoc0Hiz2vYh/yqr5UedSFDY1R9zfWS3kfeAVm1Z1YU+ulc SBrcTPsbQisZHCF9MQsb6fuw8/3ey+xPrVwK7/E0fWuFOfH0e4bKrXnlS2wYOniOEbDz 4OvQ== X-Gm-Message-State: APjAAAVT2MM3QFxlKvrFMkDfB2MYQ1p/5tMlGHL8Lct4YJDhfzVS9DMo n4ZDkwyKmP5PsSnnbNvfEh+Nsw== X-Google-Smtp-Source: APXvYqxXR8o25+joEz8dWnEvGQtXoSvqHBfBQrELC7mD18i66AQbkc7ukB5DWxdVHkw2m6ZrP3zj7A== X-Received: by 2002:a17:902:d894:: with SMTP id b20mr4696828plz.318.1553188699978; Thu, 21 Mar 2019 10:18:19 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id z6sm20953866pgo.31.2019.03.21.10.18.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Mar 2019 10:18:19 -0700 (PDT) From: Evan Green To: Kishon Vijay Abraham I Cc: Stephen Boyd , Marc Gonzalez , Can Guo , Vivek Gautam , Douglas Anderson , Asutosh Das , Evan Green , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland Subject: [PATCH v5 3/8] dt-bindings: phy: qcom-ufs: Add resets property Date: Thu, 21 Mar 2019 10:17:55 -0700 Message-Id: <20190321171800.104681-4-evgreen@chromium.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190321171800.104681-1-evgreen@chromium.org> References: <20190321171800.104681-1-evgreen@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a resets property to the PHY that represents the PHY reset register in the UFS controller itself. This better describes the complete specification of the PHY, and allows the PHY to perform its initialization in a single function, rather than relying on back-channel sequencing of initialization through the PHY framework. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - Added resets to example (Stephen). Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt index 21d9a93db2e9..fd59f93e9556 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt @@ -29,6 +29,7 @@ Optional properties: - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply +- resets : specifies the PHY reset in the UFS controller Example: @@ -51,9 +52,11 @@ Example: <&clock_gcc clk_ufs_phy_ldo>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; + resets = <&ufshc 0>; }; - ufshc@fc598000 { + ufshc: ufshc@fc598000 { + #reset-cells = <1>; ... phys = <&ufsphy1>; phy-names = "ufsphy";