From patchwork Wed Mar 6 10:20:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 1052235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-497442-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="AViZ3C39"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sMu2JqL6"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44DqXW29R5z9s70 for ; Wed, 6 Mar 2019 21:20:43 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=EmX Trrie+WyNcPYvdFe+PHB8yo9p2t04iMyQ2Vuh+CpybfTbndV92MG7tY7rLt9bZer yXY2tALx3n+9+m9EmzITcbNPkj/TD6V0WapqZevTTaDeTbcXa7Rzw/corCvku8sz IiGAqmrvflHJfczbHI4tX+Bbo3WzC9rl8g55g3hs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=6Q/hd36hm d1M9RI1Qj8gKGkhZfo=; b=AViZ3C391ug+/HEXwUfOCF5x2u4QGdISlXsdPJtRN wDT33qImYs9IZbAlhD+LKVLaWPhP+wGKRSJJNEnIAqft0fAlwXq8A1E0G+aE0lBZ TspHPcS2aPJPEwo/OaYEvCbjv1liKVXdZ1P+1xSpiH/VGWwzJ8BRpNMWA3oTug1V +k= Received: (qmail 102232 invoked by alias); 6 Mar 2019 10:20:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 102131 invoked by uid 89); 6 Mar 2019 10:20:21 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=allocates, calculations, employ X-HELO: mail-yw1-f51.google.com Received: from mail-yw1-f51.google.com (HELO mail-yw1-f51.google.com) (209.85.161.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 06 Mar 2019 10:20:18 +0000 Received: by mail-yw1-f51.google.com with SMTP id o184so9506077ywo.5 for ; Wed, 06 Mar 2019 02:20:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hqt/BflRNnyIc+A7GeyieTKPh7c/WGt1h+Ir1kztTE8=; b=sMu2JqL65Bp2gNBRBv3g/khyqKQLMlmbiWwX+BvFApzgrprh6PSZJW2BTT14c1J1yo 2bNMgT9MdN4CHbaQEWsXQ/0exzxZ3mD6ZV92KCGc/ERr0iIWuwhQOcYpqm9/2CJ24mhD j2hrc3IJuLTtMaj8t8YLn657d7XCOVBbpiH5MK0OCTAClhf3GRfUjGvWrNZt1K6fTTLh 1w4GI2td8JBZXS+UPFg9zVcgzYwheSSkO6s50ImypYdRDT/7WRlvivhRKuQhzY0yP1IU l0vP/pcpfpE+V31MmWFBZt8J3qVjOw4SxSlIBCeFjFuAM7/0MJZDhddRVOYrB00/rCOr 9+cQ== Received: from localhost.localdomain ([193.187.151.25]) by smtp.gmail.com with ESMTPSA id d85sm403718ywd.96.2019.03.06.02.20.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Mar 2019 02:20:15 -0800 (PST) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: fbedard@synopsys.com, andrew.burgess@embecosm.com, claziss@synopsys.com Subject: [PATCH 1/5] [ARC] Introduce ADJUST_REG_ALLOC_ORDER. Date: Wed, 6 Mar 2019 12:20:01 +0200 Message-Id: <20190306102005.15413-2-claziss@gmail.com> In-Reply-To: <20190306102005.15413-1-claziss@gmail.com> References: <20190306102005.15413-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes The ARC port is changing the allocation order in the arc_conditional_register_usage function, but this is not the proper way. Thus, we employ ADJUST_REG_ALLOC_ORDER hook for this task. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc-protos.h (arc_adjust_reg_alloc_order): Declare. * config/arc/arc.c (arc_conditional_register_usage): Remove all reg_alloc_order references. (size_alloc_order): Define. (arc_adjust_reg_alloc_order): New function. * config/arc/arc.h (REG_ALLOC_ORDER): Proper define the register order. (ADJUST_REG_ALLOC_ORDER): Define. (HONOR_REG_ALLOC_ORDER): Likewise. --- gcc/config/arc/arc-protos.h | 1 + gcc/config/arc/arc.c | 67 +++++++++++-------------------------- gcc/config/arc/arc.h | 33 ++++++++++++++---- 3 files changed, 47 insertions(+), 54 deletions(-) diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h index 1362b41f101..8f0f197f14a 100644 --- a/gcc/config/arc/arc-protos.h +++ b/gcc/config/arc/arc-protos.h @@ -47,6 +47,7 @@ extern unsigned int arc_compute_function_type (struct function *); extern bool arc_is_uncached_mem_p (rtx); extern bool gen_operands_ldd_std (rtx *operands, bool load, bool commute); extern bool arc_check_multi (rtx, bool); +extern void arc_adjust_reg_alloc_order (void); #endif /* RTX_CODE */ extern unsigned int arc_compute_frame_size (int); diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 9938a774d91..0b18e677735 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1807,54 +1807,6 @@ arc_conditional_register_usage (void) warning (0, "multiply option implies r%d is fixed", regno); fixed_regs [regno] = call_used_regs[regno] = 1; } - if (TARGET_Q_CLASS) - { - if (optimize_size) - { - reg_alloc_order[0] = 0; - reg_alloc_order[1] = 1; - reg_alloc_order[2] = 2; - reg_alloc_order[3] = 3; - reg_alloc_order[4] = 12; - reg_alloc_order[5] = 13; - reg_alloc_order[6] = 14; - reg_alloc_order[7] = 15; - reg_alloc_order[8] = 4; - reg_alloc_order[9] = 5; - reg_alloc_order[10] = 6; - reg_alloc_order[11] = 7; - reg_alloc_order[12] = 8; - reg_alloc_order[13] = 9; - reg_alloc_order[14] = 10; - reg_alloc_order[15] = 11; - } - else - { - reg_alloc_order[2] = 12; - reg_alloc_order[3] = 13; - reg_alloc_order[4] = 14; - reg_alloc_order[5] = 15; - reg_alloc_order[6] = 1; - reg_alloc_order[7] = 0; - reg_alloc_order[8] = 4; - reg_alloc_order[9] = 5; - reg_alloc_order[10] = 6; - reg_alloc_order[11] = 7; - reg_alloc_order[12] = 8; - reg_alloc_order[13] = 9; - reg_alloc_order[14] = 10; - reg_alloc_order[15] = 11; - } - } - if (TARGET_SIMD_SET) - { - int i; - for (i = ARC_FIRST_SIMD_VR_REG; i <= ARC_LAST_SIMD_VR_REG; i++) - reg_alloc_order [i] = i; - for (i = ARC_FIRST_SIMD_DMA_CONFIG_REG; - i <= ARC_LAST_SIMD_DMA_CONFIG_REG; i++) - reg_alloc_order [i] = i; - } /* Reduced configuration: don't use r4-r9, r16-r25. */ if (TARGET_RF16) @@ -11454,6 +11406,25 @@ gen_operands_ldd_std (rtx *operands, bool load, bool commute) return false; } +/* This order of allocation is used when we compile for size. It + allocates first the registers which are most probably to end up in + a short instruction. */ +static const int size_alloc_order[] = +{ + 0, 1, 2, 3, 12, 13, 14, 15, + 4, 5, 6, 7, 8, 9, 10, 11 +}; + +/* Adjust register allocation order when compiling for size. */ +void +arc_adjust_reg_alloc_order (void) +{ + const int arc_default_alloc_order[] = REG_ALLOC_ORDER; + memcpy (reg_alloc_order, arc_default_alloc_order, sizeof (reg_alloc_order)); + if (optimize_size) + memcpy (reg_alloc_order, size_alloc_order, sizeof (size_alloc_order)); +} + #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index fbe71278346..90420a9d474 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -361,7 +361,6 @@ if (GET_MODE_CLASS (MODE) == MODE_INT \ By default, the extension registers are not available. */ /* Present implementations only have VR0-VR23 only. */ -/* ??? FIXME: r27 and r31 should not be fixed registers. */ #define FIXED_REGISTERS \ { 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -422,12 +421,34 @@ if (GET_MODE_CLASS (MODE) == MODE_INT \ /* If defined, an initializer for a vector of integers, containing the numbers of hard registers in the order in which GCC should prefer to use them (from most preferred to least). */ -#define REG_ALLOC_ORDER \ -{ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \ +#define REG_ALLOC_ORDER \ +{ \ + /* General registers. */ \ + 2, 3, 12, 13, 14, 15, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, \ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 30, \ + /* Extension core registers. */ \ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ - 27, 28, 29, 30, 31, 63} + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ + /* VR regs. */ \ + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ + 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \ + 124, 125, 126, 127, \ + /* DMA registers. */ \ + 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, \ + 142, 143, \ + /* Register not used for general use. */ \ + 62, FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ + SP_REG, ILINK1_REG, RETURN_ADDR_REGNUM, LP_COUNT, CC_REG, PCL_REG \ +} + +/* Use different register alloc ordering for Thumb. */ +#define ADJUST_REG_ALLOC_ORDER arc_adjust_reg_alloc_order () + +/* Tell IRA to use the order we define rather than messing it up with its + own cost calculations. */ +#define HONOR_REG_ALLOC_ORDER 1 /* Internal macros to classify a register number as to whether it's a general purpose register for compact insns (r0-r3,r12-r15), or From patchwork Wed Mar 6 10:20:02 2019 Content-Type: text/plain; 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Date: Wed, 6 Mar 2019 12:20:02 +0200 Message-Id: <20190306102005.15413-3-claziss@gmail.com> In-Reply-To: <20190306102005.15413-1-claziss@gmail.com> References: <20190306102005.15413-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.opt (mcode-density-frame): Get the inital value from TARGET_CODE_DENSITY_FRAME_DEFAULT. * config/arc/elf.h (TARGET_CODE_DENSITY_FRAME_DEFAULT): Define it to 1. * config/arc/linux.h (TARGET_CODE_DENSITY_FRAME_DEFAULT): Define it to 0. --- gcc/config/arc/arc.c | 5 ++++- gcc/config/arc/arc.md | 20 ++++++++++---------- gcc/config/arc/arc.opt | 2 +- gcc/config/arc/elf.h | 4 ++++ gcc/config/arc/linux.h | 4 ++++ 5 files changed, 23 insertions(+), 12 deletions(-) diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 0b18e677735..9e086477027 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1292,6 +1292,9 @@ arc_override_options (void) if (arc_size_opt_level == 3) optimize_size = 1; + if (TARGET_V2 && optimize_size && (ATTRIBUTE_PCS == 2)) + TARGET_CODE_DENSITY_FRAME = 1; + if (flag_pic) { /* If we had SDATA enabled, still don't use GP when pic is @@ -3188,7 +3191,7 @@ arc_save_callee_enter (unsigned int gmask, reg = gen_rtx_SET (stack_pointer_rtx, plus_constant (Pmode, stack_pointer_rtx, - nregs * UNITS_PER_WORD)); + -nregs * UNITS_PER_WORD)); RTX_FRAME_RELATED_P (reg) = 1; XVECEXP (insn, 0, indx++) = reg; off = nregs * UNITS_PER_WORD; diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 54d073107a8..c64a7fdb653 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -6442,7 +6442,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" (plus:SI (reg:SI SP_REG) (match_operand 1 "immediate_operand" ""))) (set (mem:SI (plus:SI (reg:SI SP_REG) - (match_dup 1))) + (match_operand 2 "immediate_operand" ""))) (reg:SI 13))])] "TARGET_CODE_DENSITY" { @@ -6450,14 +6450,14 @@ core_3, archs4x, archs4xd, archs4xd_slow" rtx tmp = XVECEXP (operands[0], 0, len - 1); if (MEM_P (XEXP (tmp, 0))) { - operands[2] = XEXP (tmp, 1); - return "enter_s\\t{r13-%2} ; sp=sp-%1"; + operands[3] = XEXP (tmp, 1); + return "enter_s\\t{r13-%3} ; sp=sp+(%1)"; } else { tmp = XVECEXP (operands[0], 0, len - 3); - operands[2] = XEXP (tmp, 1); - return "enter_s\\t{r13-%2, fp} ; sp=sp-%1"; + operands[3] = XEXP (tmp, 1); + return "enter_s\\t{r13-%3, fp} ; sp=sp+(%1)"; } } [(set_attr "type" "call_no_delay_slot") @@ -6469,7 +6469,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" (plus:SI (reg:SI SP_REG) (match_operand 1 "immediate_operand" ""))) (set (mem:SI (plus:SI (reg:SI SP_REG) - (match_dup 1))) + (match_operand 2 "immediate_operand" ""))) (reg:SI RETURN_ADDR_REGNUM))])] "TARGET_CODE_DENSITY" { @@ -6477,14 +6477,14 @@ core_3, archs4x, archs4xd, archs4xd_slow" rtx tmp = XVECEXP (operands[0], 0, len - 1); if (MEM_P (XEXP (tmp, 0))) { - operands[2] = XEXP (tmp, 1); - return "enter_s\\t{r13-%2, blink} ; sp=sp-%1"; + operands[3] = XEXP (tmp, 1); + return "enter_s\\t{r13-%3, blink} ; sp=sp+(%1)"; } else { tmp = XVECEXP (operands[0], 0, len - 3); - operands[2] = XEXP (tmp, 1); - return "enter_s\\t{r13-%2, fp, blink} ; sp=sp-%1"; + operands[3] = XEXP (tmp, 1); + return "enter_s\\t{r13-%3, fp, blink} ; sp=sp+(%1)"; } } [(set_attr "type" "call_no_delay_slot") diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index a5271cbbceb..567df30951f 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -537,5 +537,5 @@ Target Report Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX) Enable use of BI/BIH instructions when available. mcode-density-frame -Target Report Var(TARGET_CODE_DENSITY_FRAME) +Target Report Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT) Enable ENTER_S and LEAVE_S opcodes for ARCv2. diff --git a/gcc/config/arc/elf.h b/gcc/config/arc/elf.h index 8f9bec05606..651741f3342 100644 --- a/gcc/config/arc/elf.h +++ b/gcc/config/arc/elf.h @@ -98,3 +98,7 @@ along with GCC; see the file COPYING3. If not see fixed_regs[GP_REG] = 0; \ arc_regno_reg_class[GP_REG] = GENERAL_REGS; \ } + +/* Enter/Leave ops are default on for elf targets. */ +#undef TARGET_CODE_DENSITY_FRAME_DEFAULT +#define TARGET_CODE_DENSITY_FRAME_DEFAULT 0 diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h index 6c8a7b46296..270ca907d87 100644 --- a/gcc/config/arc/linux.h +++ b/gcc/config/arc/linux.h @@ -133,3 +133,7 @@ along with GCC; see the file COPYING3. If not see fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \ emit_library_call (fun, LCT_NORMAL, VOIDmode, rt, Pmode); \ } + +/* Enter/Leave ops are default off for linux targets. */ +#undef TARGET_CODE_DENSITY_FRAME_DEFAULT +#define TARGET_CODE_DENSITY_FRAME_DEFAULT 0 From patchwork Wed Mar 6 10:20:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 1052237 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-497444-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="cW5Q/QOb"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Ca5hPSZ5"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44DqXw4Xw0z9s9T for ; Wed, 6 Mar 2019 21:21:04 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=qw3 CB1XiJVSGdFV4h5bFWOOn2ztlFKOwm4j1AuOSdheFC7A9DqgtADwC7luSZuiIHQn 6WLTWwx9z4nuwwCoDphSKwWmtRtO9419Jb039l1EoDejfb1mWx5zSKmbtvLdBSTn fORhwHpiT/RSJiTOdFWoGkVzqKspEBiZriW5DynA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=5f6jygDgh D7d3jN8t0wOqfeYxks=; b=cW5Q/QOb9U/3xJR+hNh4ZCY4VIvat0RPCHy/4agcW YShJ/ftHCx6fJRC5EsdGEfAHJutaN2GB3G7qCycCGjO/oP31HJz8gtxL+mp3TsqR yRDQjCmazUPa77PL/PJ1poLeFPPWPFOme96Dzq3tCXbzdOVX57+++Klplfdyhnhg IA= Received: (qmail 102769 invoked by alias); 6 Mar 2019 10:20:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 102472 invoked by uid 89); 6 Mar 2019 10:20:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:specula, H*MI:sk:2019030, HContent-Transfer-Encoding:8bit X-HELO: mail-yw1-f54.google.com Received: from mail-yw1-f54.google.com (HELO mail-yw1-f54.google.com) (209.85.161.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 06 Mar 2019 10:20:21 +0000 Received: by mail-yw1-f54.google.com with SMTP id c67so9503731ywa.7 for ; Wed, 06 Mar 2019 02:20:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ePyqMe+08g6YXel3kGl1iA40PtkjOndLsk9t0naVGi8=; b=Ca5hPSZ5y20WDmUnuf3NeH081jd2CHOMiSuRc2KrXZ4k8kCPFRSj9TyhodfdHk9d2I 5wn3iEwI2SblFavquYmVnZ7AAGtVyqCLHqN9x8L+F3VHzyNNLJyENXbO/ctjrfZf3tsN asFyIpefv2MURMc2hVWm+I/ojhO8VA0W+mAG4TAiwiFf2o9TQwT3Crf0wCaoDntCzcv5 aQgUne6VMNmVbIOl5c8ybD1FIqa7odtwWyEBxkRw71Wc6b1IQ2tN/GjMZJtFw2ftS2I2 F7HTSPC1I71gAXe0ZtvMUmet95YiFmhARHqE/p9kBg4wPynx5l2jn39vQkvUqqsV+v5m fPzQ== Received: from localhost.localdomain ([193.187.151.25]) by smtp.gmail.com with ESMTPSA id d85sm403718ywd.96.2019.03.06.02.20.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Mar 2019 02:20:19 -0800 (PST) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: fbedard@synopsys.com, andrew.burgess@embecosm.com, claziss@synopsys.com Subject: [PATCH 3/5] [ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE. Date: Wed, 6 Mar 2019 12:20:03 +0200 Message-Id: <20190306102005.15413-4-claziss@gmail.com> In-Reply-To: <20190306102005.15413-1-claziss@gmail.com> References: <20190306102005.15413-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.c (TARGET_HAVE_SPECULATION_SAFE_VALUE): Define. --- gcc/config/arc/arc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 9e086477027..a3a013e90e1 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -11440,6 +11440,9 @@ arc_adjust_reg_alloc_order (void) #undef TARGET_ASM_TRAMPOLINE_TEMPLATE #define TARGET_ASM_TRAMPOLINE_TEMPLATE arc_asm_trampoline_template +#undef TARGET_HAVE_SPECULATION_SAFE_VALUE +#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-arc.h" From patchwork Wed Mar 6 10:20:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 1052238 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-497445-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="e5uBSiAZ"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vaeANIq5"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44DqY82lsJz9s70 for ; Wed, 6 Mar 2019 21:21:16 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=qdo PSnIBll78cOW6i6G3nmDQfxDYdzbzfWum9ieE/P2MrAEtiaZPGz+31M/8uzvWsW/ D78xg5s8FKFQCWcPQmw8zG7tqY1ETdGiT4U9qvQiu0umx2IThePcUVS6x9aA+9Wb 46vspbJYoODMeBB8gB9rgR5+EQQMDj4GK46CQbNY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=p9Iox9guR /VLZS6c/vzc3Z5c0zU=; b=e5uBSiAZevI7Z88czIlLQwKpc6ET4lsIHhW0ms0I3 /ld7mISBW1JxU5CRNe19/rHQo71NvNhyg1gWknZr/+wZFfxkAwIwV3rVFgaZ674n euyvEDkwTJd4YaEBHNXr4O5hMSZI7oRkophBGoOooF5kyrtlqBeXu4jr3Gj9Mx/v SA= Received: (qmail 102793 invoked by alias); 6 Mar 2019 10:20:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 102695 invoked by uid 89); 6 Mar 2019 10:20:24 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=UD:cl, Hx-languages-length:994, H*MI:sk:2019030, HContent-Transfer-Encoding:8bit X-HELO: mail-yw1-f47.google.com Received: from mail-yw1-f47.google.com (HELO mail-yw1-f47.google.com) (209.85.161.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 06 Mar 2019 10:20:23 +0000 Received: by mail-yw1-f47.google.com with SMTP id u205so9539142ywe.1 for ; Wed, 06 Mar 2019 02:20:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B5yjViYyS900Zo9/Bst4i18cHY+9ZgmYE8fAUcMMss4=; b=vaeANIq5peNe44gimYiITRZhO4ixnINXtkgaAE6yhsxYCPuKr4lyYuTONT4w4MR3bR /Wmxt5ERcvpxSlgT3te+MZbNe7TBOhzzUY/gkWJDPiHROxr3OaE3mv1xvZ7vAWXe908e /ChJVaElLAyEHapFnETHr0CIVjTwaFCsnl6MGJukUeJz6TTNTbFYSPQ/f8xWLaJnKdpA JymbfDsVd9cxmmm5rFWWCB6terT2iE6jVcQPsn7BG5vJWTXxKmWjzkhUSDgxBPHSSrDM EW5yDFLXKhtGh8OCnG4lqFgLX1LsjPPWIZCDQCftWWxXseJjkE8JZbxskUK9Feyw0hh4 81Hw== Received: from localhost.localdomain ([193.187.151.25]) by smtp.gmail.com with ESMTPSA id d85sm403718ywd.96.2019.03.06.02.20.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Mar 2019 02:20:20 -0800 (PST) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: fbedard@synopsys.com, andrew.burgess@embecosm.com, claziss@synopsys.com Subject: [PATCH 4/5] [ARC] Fix tst_movb pattern. Date: Wed, 6 Mar 2019 12:20:04 +0200 Message-Id: <20190306102005.15413-5-claziss@gmail.com> In-Reply-To: <20190306102005.15413-1-claziss@gmail.com> References: <20190306102005.15413-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.md (tst_movb): Fix constraint. --- gcc/config/arc/arc.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index c64a7fdb653..1e64331f397 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -958,10 +958,10 @@ core_3, archs4x, archs4xd, archs4xd_slow" (match_operand 0 "cc_register" "") (match_operator 4 "zn_compare_operator" [(and:SI - (match_operand:SI 1 "register_operand" "%Rcq,Rcq, c, c, c, c,Rrq, 3, c") + (match_operand:SI 1 "register_operand" "%Rcq,Rcq, c, c, c, c,Rrq,Rrq, c") (match_operand:SI 2 "nonmemory_operand" "Rcq,C0p,cI,C1p,Ccp,Chs,Cbf,Cbf,???Cal")) (const_int 0)])) - (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,Rrq,Rrq,c"))] + (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,Rrq,1,c"))] "TARGET_NPS_BITOPS" "movb.f.cl %3,%1,%p2,%p2,%s2" "TARGET_NPS_BITOPS && reload_completed From patchwork Wed Mar 6 10:20:05 2019 Content-Type: text/plain; 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Date: Wed, 6 Mar 2019 12:20:05 +0200 Message-Id: <20190306102005.15413-6-claziss@gmail.com> In-Reply-To: <20190306102005.15413-1-claziss@gmail.com> References: <20190306102005.15413-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes xxxx-xx-xx Claudiu Zissulescu * config/arc/arc-protos.h (arc_register_move_cost): Remove. * config/arc/arc.c (arc_register_move_cost): Re-purpose it to implement target hook. (arc_memory_move_cost): New function. (TARGET_REGISTER_MOVE_COST): Define. (TARGET_MEMORY_MOVE_COST): Likewise. * config/arc/arc.h (REGISTER_MOVE_COST): Remove. (MEMORY_MOVE_COST): Likewise. --- gcc/config/arc/arc-protos.h | 2 -- gcc/config/arc/arc.c | 26 ++++++++++++++++++++++++-- gcc/config/arc/arc.h | 11 ----------- 3 files changed, 24 insertions(+), 15 deletions(-) diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h index 8f0f197f14a..ac0de6b2874 100644 --- a/gcc/config/arc/arc-protos.h +++ b/gcc/config/arc/arc-protos.h @@ -68,8 +68,6 @@ extern bool arc_is_shortcall_p (rtx); extern bool valid_brcc_with_delay_p (rtx *); extern bool arc_ccfsm_cond_exec_p (void); struct secondary_reload_info; -extern int arc_register_move_cost (machine_mode, enum reg_class, - enum reg_class); extern rtx disi_highpart (rtx); extern int arc_adjust_insn_length (rtx_insn *, int, bool); extern int arc_corereg_hazard (rtx, rtx); diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index a3a013e90e1..50977704c45 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -8686,9 +8686,11 @@ arc_preserve_reload_p (rtx in) && !((INTVAL (XEXP (in, 1)) & 511))); } -int +/* Implement TARGET_REGISTER_MOVE_COST. */ + +static int arc_register_move_cost (machine_mode, - enum reg_class from_class, enum reg_class to_class) + reg_class_t from_class, reg_class_t to_class) { /* Force an attempt to 'mov Dy,Dx' to spill. */ if ((TARGET_ARC700 || TARGET_EM) && TARGET_DPFP @@ -11428,6 +11430,20 @@ arc_adjust_reg_alloc_order (void) memcpy (reg_alloc_order, size_alloc_order, sizeof (size_alloc_order)); } +/* Implement TARGET_MEMORY_MOVE_COST. */ + +static int +arc_memory_move_cost (machine_mode mode, + reg_class_t rclass ATTRIBUTE_UNUSED, + bool in ATTRIBUTE_UNUSED) +{ + if ((GET_MODE_SIZE (mode) <= UNITS_PER_WORD) + || ((GET_MODE_SIZE (mode) <= UNITS_PER_WORD * 2) && TARGET_LL64)) + return 6; + + return (2 * GET_MODE_SIZE (mode)); +} + #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p @@ -11443,6 +11459,12 @@ arc_adjust_reg_alloc_order (void) #undef TARGET_HAVE_SPECULATION_SAFE_VALUE #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed +#undef TARGET_REGISTER_MOVE_COST +#define TARGET_REGISTER_MOVE_COST arc_register_move_cost + +#undef TARGET_MEMORY_MOVE_COST +#define TARGET_MEMORY_MOVE_COST arc_memory_move_cost + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-arc.h" diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index 90420a9d474..46ca2dde413 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -925,17 +925,6 @@ arc_select_cc_mode (OP, X, Y) /* Costs. */ -/* Compute extra cost of moving data between one register class - and another. */ -#define REGISTER_MOVE_COST(MODE, CLASS, TO_CLASS) \ - arc_register_move_cost ((MODE), (CLASS), (TO_CLASS)) - -/* Compute the cost of moving data between registers and memory. */ -/* Memory is 3 times as expensive as registers. - ??? Is that the right way to look at it? */ -#define MEMORY_MOVE_COST(MODE,CLASS,IN) \ -(GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12) - /* The cost of a branch insn. */ /* ??? What's the right value here? Branches are certainly more expensive than reg->reg moves. */