From patchwork Wed Feb 13 23:25:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1041698 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="ZRWrc1MW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 440Fyg4klPz9sMr for ; Thu, 14 Feb 2019 10:26:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389763AbfBMX0T (ORCPT ); Wed, 13 Feb 2019 18:26:19 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:44271 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389702AbfBMX0S (ORCPT ); Wed, 13 Feb 2019 18:26:18 -0500 Received: by mail-pl1-f196.google.com with SMTP id p4so1972773plq.11 for ; Wed, 13 Feb 2019 15:26:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zVtYgVjd/xRzchJj83lLQZj8nZX16NvmAHavBWvuhDY=; b=ZRWrc1MWCe28Sf4cWnA4KkYW2AVIFLMTieUDT4B+cS52QenfIY3gKhtcFDpHwZS1na 0oNq9FWPfgffRBHMNFwb8xjNdB39YvuZ1D/jKrB1v79DbpsWkuUynY6/8q3LWVEah5NN 0gm+I9E1BXopN8kZZoGLwS7LtupMKUcptj1ss= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zVtYgVjd/xRzchJj83lLQZj8nZX16NvmAHavBWvuhDY=; b=qHt5bprZePL54wSm6yLbMWC7frkS/p1oA5iI5SJOnWUwA3ojFQnr9i2HybU159t/I6 cRp0DGeOnsF4bPZsmTTogUjGB4xkkE4ZiKOIfI4oocpDh+EqzhBQNLGkRelo8ZIoKFzA 1gLjQNCZf+aT4IbDC16DQYsgYMbdhwoxIa1kKqR0Vg3WvijhxLjcivQdmZGIQrWsHw7g M49jrUVZFKxtMlEzg4h+9mfsQOnHRhQXU2v3CUAVj/+YqJJUN//b6LYUEERbec7BJk8o NpB3eHDaXCTaCft3yfyNnbyXXwP3bzso83UiriuAmiPAd9OsR8ZXnt4A2dMrfo4ox7WH J1BA== X-Gm-Message-State: AHQUAuatwlpwxH+88o2lgyI5YObdfnpzo3X21GdpLLGiE7oPotZaV8DD C9SiD5liKFzknJTI5ppiy0Sfnw== X-Google-Smtp-Source: AHgI3IZJoQOlHjdGf+UsBpTh6Gif7TXeZK7nMMGs8WkyFT4Kf0Obam1yseqPmfZ5ISVKGYWQ+pIb7g== X-Received: by 2002:a17:902:9a03:: with SMTP id v3mr734284plp.187.1550100378255; Wed, 13 Feb 2019 15:26:18 -0800 (PST) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id d129sm560660pfc.31.2019.02.13.15.26.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Feb 2019 15:26:17 -0800 (PST) From: Evan Green To: Andy Gross , Kishon Vijay Abraham I Cc: Stephen Boyd , Marc Gonzalez , Can Guo , Vivek Gautam , Douglas Anderson , Asutosh Das , Evan Green , Rob Herring , devicetree@vger.kernel.org, liwei , linux-kernel@vger.kernel.org, Subhash Jadavani , Rob Herring , "Martin K. Petersen" , Mark Rutland Subject: [PATCH v4 1/8] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers Date: Wed, 13 Feb 2019 15:25:19 -0800 Message-Id: <20190213232526.26995-2-evgreen@chromium.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190213232526.26995-1-evgreen@chromium.org> References: <20190213232526.26995-1-evgreen@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable Qualcomm UFS controllers to expose the PHY reset via a reset controller. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 8cf59452c675..e2460b666ae4 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -47,6 +47,8 @@ Optional properties: -lanes-per-direction : number of lanes available per direction - either 1 or 2. Note that it is assume same number of lanes is used both directions at once. If not specified, default is 2 lanes per direction. +- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose + PHY reset from the UFS controller. - resets : reset node register - reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP. @@ -76,4 +78,5 @@ Example: reset-names = "rst"; phys = <&ufsphy1>; phy-names = "ufsphy"; + #reset-cells = <1>; }; From patchwork Wed Feb 13 23:25:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1041700 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="axupwHCW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 440FzX19K8z9sN4 for ; Thu, 14 Feb 2019 10:27:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390292AbfBMX0W (ORCPT ); Wed, 13 Feb 2019 18:26:22 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:40312 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389298AbfBMX0V (ORCPT ); Wed, 13 Feb 2019 18:26:21 -0500 Received: by mail-pl1-f196.google.com with SMTP id bj4so1976365plb.7 for ; Wed, 13 Feb 2019 15:26:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tTrz5iCREgQGXYUDyQ4vY7F8M1o2Gjn3QDNWgZd/TLo=; b=axupwHCWl0wuJEKGzGgbKByB637wsRkny0N9pdp60VtrWi34+nGnjhpAQSlk3sCdBx aeZzDIkbpfCrnqre4f9l3nhqIBts3uiC/8hMuwFIRdstH7TR4xzfFj8X2H2sECdB6LoO OjjAhCOQfTyMV4i9z+MxqC9hM2URbttTmmZp8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tTrz5iCREgQGXYUDyQ4vY7F8M1o2Gjn3QDNWgZd/TLo=; b=MXH/0+7sVrjCpz3F0tvte5aKCHmHrpGKh2vvVoU8+DAF1xbTqnTTl9OxQRJ3mZKMTy pDSi6Z3QqTkPe9+XX8PUHYhCi3b6/yUyBQyE9K2O5dmvicXnRPZSXE5C0mu0xDY/difr pkvXNra+HiAa5kGO4qTNDCDGXx7s0SutcalMlAtEtDkhcUxc3lich1Gq2NvlDlmz/lhy A/KEpPCpJ6aMz5ngTAX8zo+09Ezd85nPVfNQ+mH24Ei5XSoXAdaKlfslpimMdAoI5/uS 0JmPUoDenZ0ovsxC8Ws5DbbHam34/X2bc3OxEUyTykW5+dSBCg0rL/LcIwTFJ4vhfkQv MHsQ== X-Gm-Message-State: AHQUAua/Qgm1k5oDkXSuHSi4WvMzeSaRQzEexC4zwPd1f5Y3NXghAtXO Zwrv0hxON5JAEN9RfZ/Znbn7rA== X-Google-Smtp-Source: AHgI3IZcwFyihgNlx4RQ6DFsU8JJ7gdAfJxyxUpSK4QBk41uq7EShRRB47nqsWSuGstLSo4O1A07Yw== X-Received: by 2002:a17:902:ba90:: with SMTP id k16mr784980pls.214.1550100380615; Wed, 13 Feb 2019 15:26:20 -0800 (PST) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id d129sm560660pfc.31.2019.02.13.15.26.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Feb 2019 15:26:19 -0800 (PST) From: Evan Green To: Andy Gross , Kishon Vijay Abraham I Cc: Stephen Boyd , Marc Gonzalez , Can Guo , Vivek Gautam , Douglas Anderson , Asutosh Das , Evan Green , Rob Herring , devicetree@vger.kernel.org, Mark Rutland , Rob Herring , linux-kernel@vger.kernel.org Subject: [PATCH v4 2/8] dt-bindings: phy-qcom-qmp: Add UFS PHY reset Date: Wed, 13 Feb 2019 15:25:20 -0800 Message-Id: <20190213232526.26995-3-evgreen@chromium.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190213232526.26995-1-evgreen@chromium.org> References: <20190213232526.26995-1-evgreen@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a required reset to the SDM845 UFS phy to express the PHY reset bit inside the UFS controller register space. Before this change, this reset was not expressed in the DT, and the driver utilized two different callbacks (phy_init and phy_poweron) to implement a two-phase initialization procedure that involved deasserting this reset between init and poweron. This abused the two callbacks and diluted their purpose. That scheme does not work as regulators cannot be turned off in phy_poweroff because they were turned on in init, rather than poweron. The net result is that regulators are left on in suspend that shouldn't be. This new scheme gives the UFS reset to the PHY, so that it can fully initialize itself in a single callback. We can then turn regulators on during poweron and off during poweroff. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- I realize I'm not supposed to add a required property after the fact, but given that the UFS DT nodes that would use this binding are not yet upstream (and this would be the first), I was hoping to squeak by. Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 5d181fc3cc18..4a78ba8b85bc 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -59,7 +59,8 @@ Required properties: one for each entry in reset-names. - reset-names: "phy" for reset of phy block, "common" for phy common block reset, - "cfg" for phy's ahb cfg block reset. + "cfg" for phy's ahb cfg block reset, + "ufsphy" for the PHY reset in the UFS controller. For "qcom,ipq8074-qmp-pcie-phy" must contain: "phy", "common". @@ -74,7 +75,8 @@ Required properties: "phy", "common". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: "phy", "common". - For "qcom,sdm845-qmp-ufs-phy": no resets are listed. + For "qcom,sdm845-qmp-ufs-phy": must contain: + "ufsphy". - vdda-phy-supply: Phandle to a regulator supply to PHY core block. - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. From patchwork Wed Feb 13 23:25:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1041699 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="R9YuU2jX"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 440FzW257Wz9sMr for ; Thu, 14 Feb 2019 10:27:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390618AbfBMX1C (ORCPT ); Wed, 13 Feb 2019 18:27:02 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:35041 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390322AbfBMX0X (ORCPT ); Wed, 13 Feb 2019 18:26:23 -0500 Received: by mail-pl1-f196.google.com with SMTP id p8so1991447plo.2 for ; Wed, 13 Feb 2019 15:26:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iFzJHslHRuN7dshluGWs7x+KZ7HWieibqhqCVGvZ6jg=; b=R9YuU2jXMWyx2mG4N66ZCHrNaWwKlmyS4uX3sY30VIgk3eGyB5pVqVnt4qUGVSApRX aKK/RpL27Pe5zuO6I8ybDUJ6N9JNCKZz2u4TGpqsXDX8Dnwvz0VA3OvoyE//uDj8tbjW SsMS5qVFiR/g8ybN7SnOwtlKDquXyrsoNVrOk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iFzJHslHRuN7dshluGWs7x+KZ7HWieibqhqCVGvZ6jg=; b=rnAsy9Y9NtHIlZ/Vy3wzB+yB1nAmEEkZPL9HzdgccRaxgaKSA1a9yBwCaaT4/AyoXX FP8Wp9U12kHv2WU1doSKNQNA1g9XTVrAdtlqEyHw31oozvuqYoAlME2sH0q61bwv+Ove aCFs85VsnKKO6FAEE9lG7Arka0YDjtaE83l/bp1S8yp+iweSCtl3621kY9eg5psMwu3t C/DbkaG6O9LNDfyiMvNVGBY/FXJ7glR1UPM+Xf/oQd0NMObPWnl8atC6UH10dXzESq5j RL3Z51RsJo+L+yrxKOymAWGvHoEjZWyrFrM5cKY2u2sSH5SMdTTTXp460Lo+dcZB3Ebh 1hbA== X-Gm-Message-State: AHQUAuaNAztY7kv2KaKPEdMWRuQxTH6+hdNl/MeTjAyW9UOkK++uuk52 lD1xCxXR+CarKmBZh1GXRgCasIH4MFY= X-Google-Smtp-Source: AHgI3Ia4uVR+Uag157wWj7qLTNfst/lpz/VJYvFyREwiwAKPub84ZOQgWxGVEwZX4fO0gx2nJ4j19Q== X-Received: by 2002:a17:902:2e01:: with SMTP id q1mr772941plb.240.1550100382818; Wed, 13 Feb 2019 15:26:22 -0800 (PST) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id d129sm560660pfc.31.2019.02.13.15.26.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Feb 2019 15:26:22 -0800 (PST) From: Evan Green To: Andy Gross , Kishon Vijay Abraham I Cc: Stephen Boyd , Marc Gonzalez , Can Guo , Vivek Gautam , Douglas Anderson , Asutosh Das , Evan Green , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland Subject: [PATCH v4 3/8] dt-bindings: phy: qcom-ufs: Add resets property Date: Wed, 13 Feb 2019 15:25:21 -0800 Message-Id: <20190213232526.26995-4-evgreen@chromium.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190213232526.26995-1-evgreen@chromium.org> References: <20190213232526.26995-1-evgreen@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a resets property to the PHY that represents the PHY reset register in the UFS controller itself. This better describes the complete specification of the PHY, and allows the PHY to perform its initialization in a single function, rather than relying on back-channel sequencing of initialization through the PHY framework. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- Changes in v4: None Changes in v3: None Changes in v2: - Added resets to example (Stephen). Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt index 21d9a93db2e9..fd59f93e9556 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt @@ -29,6 +29,7 @@ Optional properties: - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply +- resets : specifies the PHY reset in the UFS controller Example: @@ -51,9 +52,11 @@ Example: <&clock_gcc clk_ufs_phy_ldo>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; + resets = <&ufshc 0>; }; - ufshc@fc598000 { + ufshc: ufshc@fc598000 { + #reset-cells = <1>; ... phys = <&ufsphy1>; phy-names = "ufsphy";