From patchwork Thu Oct 19 09:04:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 827984 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="H0fO1StU"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yHjgT5vY3z9t41 for ; Thu, 19 Oct 2017 20:05:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 81AE0C21F50; Thu, 19 Oct 2017 09:05:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AC5E1C21E3E; Thu, 19 Oct 2017 09:05:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0CFAFC21E3E; Thu, 19 Oct 2017 09:05:03 +0000 (UTC) Received: from mail-wr0-f193.google.com (mail-wr0-f193.google.com [209.85.128.193]) by lists.denx.de (Postfix) with ESMTPS id 93FAEC21C93 for ; Thu, 19 Oct 2017 09:04:59 +0000 (UTC) Received: by mail-wr0-f193.google.com with SMTP id u40so1656141wrf.10 for ; Thu, 19 Oct 2017 02:04:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=OSPCyZS4WqlllkMIcs4b3flMHhvWotrCLx2vT417n2Q=; b=H0fO1StU6HH+LVsXxwmyx0zxhGLYe0M94tHmVS4drCiwFAa6XptXPBWaC+GxeDErEQ Bn52zmrGd87+BHEfXwv2s2mBDXpQHdRtWumSb+4Z6sT9R52pUAilqxLnIsWB//oDfrho SJR6ebHsjq9M4/5LeHCXR/2koGFWiNoI3LqR5Y9njqmzFnRPIrzItDFKY09egfaRfqtt dHkMKOnqBZ7kjoyooQRCqajOVgbhanYRqDeAtlm6Wh8XwnCDzt8nz0+2kV5Ga7CKM5dE QpkQfsiWAxy+i4p3Q4+5IRlkSyReYK0IsOyMHqu0613wzbfmwBe9bzt2RAGgYE3iAwfa DOWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=OSPCyZS4WqlllkMIcs4b3flMHhvWotrCLx2vT417n2Q=; b=CL2JJ2UOKNuJ2S/RnA1CIX2Igm9t+YnDb6gRIvBN3RmHuh2PWyKO6JWslibScxmvvU BT05gaLbZJYybXH9d84hm5mf2RH2nETX2avythiA6ibQhfdAOXonjXVFtjj9qIYnQr1f 1sQZxMPIu9hjP4Jwb02082NHXyGwvD8Y1h1qzYODnyfi9oBfnAY66WjaosZNC1/XcTlr N8VcdlB4ZzNlKw4nS+7Ko+sMvzxkS3RdZo89P3/RTVnlwDBSG0vg/oNia4x9OGVnre84 Jpge/UCWbHaC/HsoBgM3coGMBOL5BEFzEY1RS4A6zxwWk706L/F54+Hk3auDfzV8BM2o TtNw== X-Gm-Message-State: AMCzsaUj0SYOw08pXiiZlgNSnqNZc6I+CKudcdCCAatWqGKx5A2F8meK 5PXzs0GaC7bdTsps5tKzQwzvOL3FVbY= X-Google-Smtp-Source: ABhQp+RcS6lxZsWChNn2n3CTLkPVnHXRsXMkwXlaqcPfIWq+PegYoHaBT8S7tN7nQ2O6a0cKzCfIUQ== X-Received: by 10.223.172.212 with SMTP id o78mr909080wrc.6.1508403898851; Thu, 19 Oct 2017 02:04:58 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id p49sm28649080wrc.61.2017.10.19.02.04.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Oct 2017 02:04:58 -0700 (PDT) From: Neil Armstrong To: u-boot@lists.denx.de, albert.u.boot@aribaud.net, joe.hershberger@ni.com Date: Thu, 19 Oct 2017 11:04:52 +0200 Message-Id: <1508403892-22578-1-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 2.7.4 Cc: trini@konsulko.com, linux-amlogic@lists.infradead.org Subject: [U-Boot] [RFC PATCH u-boot] ARM: arch-meson: build memory banks using reported memory from registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware and a secondary BL32 firmware. Since mid-2017, the reserved memory address of the BL31 firmware was moved and grown for security reasons. But mainline U-boot and Linux has the old address and size fixed. These SoCs have a register interface to get the two firmware reserved memory start and sizes. This patch adds a dynamic memory bank redistribution according to the values in the firmware. Note that the memory address ordering between BL31 and BL32 is not etablished, so it must be determined dynamically. [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html Signed-off-by: Neil Armstrong --- arch/arm/include/asm/arch-meson/gxbb.h | 15 ++++++ arch/arm/mach-meson/board.c | 99 +++++++++++++++++++++++++++++++--- include/configs/meson-gxbb-common.h | 2 +- 3 files changed, 109 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h index 74d5290..57db37e 100644 --- a/arch/arm/include/asm/arch-meson/gxbb.h +++ b/arch/arm/include/asm/arch-meson/gxbb.h @@ -7,10 +7,25 @@ #ifndef __GXBB_H__ #define __GXBB_H__ +#define GXBB_AOBUS_BASE 0xc8100000 #define GXBB_PERIPHS_BASE 0xc8834400 #define GXBB_HIU_BASE 0xc883c000 #define GXBB_ETH_BASE 0xc9410000 +/* Always-On Peripherals registers */ +#define GXBB_AO_ADDR(off) (GXBB_AOBUS_BASE + ((off) << 2)) + +#define GXBB_AO_SEC_GP_CFG0 GXBB_AO_ADDR(0x90) +#define GXBB_AO_SEC_GP_CFG3 GXBB_AO_ADDR(0x93) +#define GXBB_AO_SEC_GP_CFG4 GXBB_AO_ADDR(0x94) +#define GXBB_AO_SEC_GP_CFG5 GXBB_AO_ADDR(0x95) + +#define GXBB_AO_MEM_SIZE_MASK 0xFFFF0000 +#define GXBB_AO_MEM_SIZE_SHIFT 16 +#define GXBB_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define GXBB_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + /* Peripherals registers */ #define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2)) diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c index e89c6aa..bd330af 100644 --- a/arch/arm/mach-meson/board.c +++ b/arch/arm/mach-meson/board.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -34,14 +36,99 @@ int dram_init(void) return 0; } +phys_size_t get_effective_memsize(void) +{ + /* Size is reported in MiB, convert it in bytes */ + return ((in_le32(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK) + >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + int dram_init_banksize(void) { - /* Reserve first 16 MiB of RAM for firmware */ - gd->bd->bi_dram[0].start = 0x1000000; - gd->bd->bi_dram[0].size = 0xf000000; - /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */ - gd->bd->bi_dram[1].start = 0x10000000; - gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000; + u32 bl31_size, bl31_start; + u32 bl32_size, bl32_start; + /* Start after first 16MiB reserved zone */ + unsigned int next = 0; + u32 last = 0x1000000; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + + reg = in_le32(GXBB_AO_SEC_GP_CFG3); + + bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK) + >> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = in_le32(GXBB_AO_SEC_GP_CFG5); + bl32_start = in_le32(GXBB_AO_SEC_GP_CFG4); + + if (bl31_size && bl31_start && bl32_size && bl32_start) { + /* Reserve memory for ARM Trusted Firmware (BL31 && BL32) */ + gd->bd->bi_dram[next].start = last; + if (bl31_start > bl32_start) + gd->bd->bi_dram[next].size = bl32_start - last; + else + gd->bd->bi_dram[next].size = bl31_start - last; + + last = gd->bd->bi_dram[next].start + + gd->bd->bi_dram[next].size; + + if (bl31_start > bl32_start) + last += bl32_size; + else + last += bl31_size; + next++; + + gd->bd->bi_dram[next].start = last; + if (bl31_start > bl32_start) + gd->bd->bi_dram[next].size = bl31_start - last; + else + gd->bd->bi_dram[next].size = bl32_start - last; + + last = gd->bd->bi_dram[next].start + + gd->bd->bi_dram[next].size; + + if (bl31_start > bl32_start) + last += bl31_size; + else + last += bl32_size; + next++; + } else if ((bl31_size && bl31_start) || (bl32_size && bl32_start)) { + /* Reserve memory for ARM Trusted Firmware (BL31 || BL32) */ + gd->bd->bi_dram[next].start = last; + if (bl31_start && bl31_size) + gd->bd->bi_dram[next].size = bl31_start - last; + else + gd->bd->bi_dram[next].size = bl32_start - last; + + last = gd->bd->bi_dram[next].start + + gd->bd->bi_dram[next].size; + + if (bl31_start && bl31_size) + last += bl31_size; + else + last += bl32_size; + + next++; + } + + /* Add remaining memory */ + gd->bd->bi_dram[next].start = last; + gd->bd->bi_dram[next].size = get_effective_memsize() - last; + next++; + + /* Reset unused banks */ + for ( ; next < CONFIG_NR_DRAM_BANKS ; ++next) { + gd->bd->bi_dram[next].start = 0; + gd->bd->bi_dram[next].size = 0; + } + return 0; } diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index d88d42d..e70fccd 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -10,7 +10,7 @@ #define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF -#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_NR_DRAM_BANKS 3 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 32 #define CONFIG_SYS_MALLOC_LEN (32 << 20)