From patchwork Thu Jan 24 08:54:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 1030370 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="Tz2BNqRk"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43lbb84hrSz9s55 for ; Thu, 24 Jan 2019 19:55:28 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7098FC21DD9; Thu, 24 Jan 2019 08:55:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 38063C21C57; Thu, 24 Jan 2019 08:55:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1C595C21C27; Thu, 24 Jan 2019 08:55:23 +0000 (UTC) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by lists.denx.de (Postfix) with ESMTPS id AF7E1C21C38 for ; Thu, 24 Jan 2019 08:55:22 +0000 (UTC) Received: by mail-wm1-f68.google.com with SMTP id g67so2103087wmd.2 for ; Thu, 24 Jan 2019 00:55:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qXB3lnVfGhOzSYngEN7oN8Qz2Fbv6lUIdwkefjdhDOI=; b=Tz2BNqRkkDMjBS3Lil/kaoPNekOFJvLDqBWNmIU/NxZRXE3nC1PuWV4algsIf5yxnB mBVirBONSpd9S4cc3x39ueuHn3Fuv0DWlwXVvgVKBFIAejsNMV68STxeG+XqJMlshI8x 003Ol79KzInSsQ+0BHLnnXCLiCvil8zAQB0OsHwCyV/U0/O588x+EBJur/s28W0/19H+ N3/SF8ZU8psun2LYVM54FOnRkSnTTLnRa8iMBwHWDHCaq4m9f3MQ4y8yujfyHuPSKhax oCvStzowQvhtfGnXS9QCQFd7rbkU6UwHJ13mYEV1S7k1sXQew5GMD/lFAvX1EYldZsqN vNRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qXB3lnVfGhOzSYngEN7oN8Qz2Fbv6lUIdwkefjdhDOI=; b=RxcvhltF52YGnBmXdFYj59/baCmT/od89ivPBXjo+eeQGITHLqgJ1n6KPayFai9vFE WFm3AAoLx4LKUa8UcAqqQNJL2LwU+BGQEpLYISNDglWrRR0v+bxAn+Zo6y+JFfbDxZjq iodKnjKJBaINHz4GZohjgF6U3CBmzT6lIjoBTrVZJlyFat1fHve/D9E1Qbm2GAKU2mn0 h9ZojC9xiOeSs5p+lbcej4SlouqhidOCCAlo01+q715bEdp0EatxaL8K7zwa/p4Xpb9K DL0RVRrtGoxE74SvARfHWfEcZGvz5gu9a8g/EH8bsz/KPzOjr5obXXsrAw4qBQsZDrPT UFjA== X-Gm-Message-State: AJcUukeQcvl87lpHjwklJXSrZeuPNEZOQJ+7uZCS9chTL0r1ZrGQoN10 4+SUtOCqiz0ijY/2zpqgwQ/EOg== X-Google-Smtp-Source: ALg8bN5U4WZyPYIyzEGQsg5FQLesYHz/162AT/x8idJkGhOK/l0/1MWgn54F50TLlDeJG0djiAv4cw== X-Received: by 2002:a1c:5656:: with SMTP id k83mr1674310wmb.125.1548320122059; Thu, 24 Jan 2019 00:55:22 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:f7a1:ce00:5105:4b7b:c922:7c6]) by smtp.gmail.com with ESMTPSA id y1sm76176327wme.1.2019.01.24.00.55.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Jan 2019 00:55:21 -0800 (PST) From: Carlo Caione To: joe.hershberger@ni.com, joseph.hershberger@ni.com, u-boot@lists.denx.de Date: Thu, 24 Jan 2019 08:54:37 +0000 Message-Id: <20190124085437.18625-1-ccaione@baylibre.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Cc: Carlo Caione Subject: [U-Boot] [PATCH v2] net: phy: realtek: Introduce quirk to mark RXC not stoppable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When EEE is supported by the PHY and the driver allows it, libphy in the kernel is configuring the PHY to stop receiving the xMII clock while it is signaling LPI. While this (usually) works fine in the kernel this is causing issues in U-Boot when rebooting from the linux kernel with this bit set (without having the possibility to reset the PHY) where the PHY suddenly stops working. A new quirk is introduced to unconditionally reset this bit. If the quirk is not enabled using the proper configuration symbol, the PHY state is not changed. Signed-off-by: Carlo Caione Acked-by: Joe Hershberger --- drivers/net/phy/Kconfig | 20 ++++++++++++++++++++ drivers/net/phy/realtek.c | 19 +++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 3dc0822d9c..631b52b1cf 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -202,6 +202,26 @@ config RTL8211X_PHY_FORCE_MASTER If unsure, say N. +config RTL8211F_PHY_FORCE_EEE_RXC_ON + bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI" + depends on PHY_REALTEK + default n + help + The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate + transitions to/from a lower power consumption level (Low Power Idle + mode) based on link utilization. When no packets are being + transmitted, the system goes to Low Power Idle mode to save power. + + Under particular circumstances this setting can cause issues where + the PHY is unable to transmit or receive any packet when in LPI mode. + The problem is caused when the PHY is configured to stop receiving + the xMII clock while it is signaling LPI. For some PHYs the bit + configuring this behavior is set by the Linux kernel, causing the + issue in U-Boot on reboot if the PHY retains the register value. + + Default n, which means that the PHY state is not changed. To work + around the issues, change this setting to y. + config PHY_SMSC bool "Microchip(SMSC) Ethernet PHYs support" diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index b3e6578df9..fa11696fe2 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -12,6 +12,7 @@ #define PHY_RTL8211x_FORCE_MASTER BIT(1) #define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2) +#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3) #define PHY_AUTONEGOTIATE_TIMEOUT 5000 @@ -75,6 +76,15 @@ static int rtl8211e_probe(struct phy_device *phydev) return 0; } +static int rtl8211f_probe(struct phy_device *phydev) +{ +#ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON + phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON; +#endif + + return 0; +} + /* RealTek RTL8211x */ static int rtl8211x_config(struct phy_device *phydev) { @@ -124,6 +134,14 @@ static int rtl8211f_config(struct phy_device *phydev) { u16 reg; + if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) { + unsigned int reg; + + reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); + reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN; + phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg); + } + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); phy_write(phydev, MDIO_DEVAD_NONE, @@ -333,6 +351,7 @@ static struct phy_driver RTL8211F_driver = { .uid = 0x1cc916, .mask = 0xffffff, .features = PHY_GBIT_FEATURES, + .probe = &rtl8211f_probe, .config = &rtl8211f_config, .startup = &rtl8211f_startup, .shutdown = &genphy_shutdown,