From patchwork Wed Jan 23 22:11:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1030211 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="JC2LKH6b"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43lKJk4yMfz9sCX for ; Thu, 24 Jan 2019 09:12:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726367AbfAWWMF (ORCPT ); Wed, 23 Jan 2019 17:12:05 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:45525 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726157AbfAWWME (ORCPT ); Wed, 23 Jan 2019 17:12:04 -0500 Received: by mail-pf1-f195.google.com with SMTP id g62so1861016pfd.12 for ; Wed, 23 Jan 2019 14:12:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QnBy3yFqLwRX55WY/zVdCOpm+/+wmQpglkGG4K9iWAk=; b=JC2LKH6bgY/tersTa9GmDGjmtc3MQzAiSCLBE4pWPCmurqPXT+MXVDkzuRODzqCD+m /gREHqEs30sFQ4E4ozamLuas3Lirbca6RlVG5nh38+sS+Apn0NkmBapRfTTX2Abb8l9z X+lPkWyIy0mFQyAUryrMCbOHS5jUwR4f8NeKE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QnBy3yFqLwRX55WY/zVdCOpm+/+wmQpglkGG4K9iWAk=; b=lCjaJrSRzM3bHavBHNFOBxB1znSMvhgg267k5raDs+So1TxsdIB1UqwGS9wM8itYvg oyORCOlXMPs4xQvCKAE6zC1kspUelD32Bpx7djwxziZ8qD+A1QitTuN0FoDwtsO2x6Ck Vv2ZJIWjt3htRZmvd/xa+03utYapsbZgso5tCoNti2Q9eADNKEU1gYLWIZE2dkSqM+aY 8VZHZ+4dtOJ6VRma+7BuYhi7JMHnutoUrD2JdaHADY2MbleC9S6h9QJGvV6qw2Fb7/L3 tTCPkhunV+fQygSYLljaw6D+JTvfpk2l3bjGlV0qMtP3Nnwen8v98+AP4qGbB3TES4+n 3SZQ== X-Gm-Message-State: AJcUukeE/b61EA79b8T1hp+xQ2X9sTOB2AEShWm89XHdyLmwlWl5z5UU U64QJh+UVFL6JKQWVDkyKAa9KA== X-Google-Smtp-Source: ALg8bN776wtxE68uoxKfmS+B3PdjVJDjmggLUklOUYvAwvjGD48uEEADg4TZR1SIe0IaELhQRdjUQg== X-Received: by 2002:a62:4e16:: with SMTP id c22mr3760419pfb.167.1548281523456; Wed, 23 Jan 2019 14:12:03 -0800 (PST) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id d18sm27927943pfj.47.2019.01.23.14.12.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 23 Jan 2019 14:12:02 -0800 (PST) From: Evan Green To: Andy Gross , Rob Herring , Kishon Vijay Abraham I Cc: Can Guo , Douglas Anderson , Asutosh Das , Stephen Boyd , Vivek Gautam , Evan Green , devicetree@vger.kernel.org, liwei , linux-kernel@vger.kernel.org, Subhash Jadavani , "Martin K. Petersen" , Mark Rutland Subject: [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers Date: Wed, 23 Jan 2019 14:11:29 -0800 Message-Id: <20190123221137.41722-2-evgreen@chromium.org> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20190123221137.41722-1-evgreen@chromium.org> References: <20190123221137.41722-1-evgreen@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable Qualcomm UFS controllers to expose the PHY reset via a reset controller. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- Fixing up this aspect of it made me notice that this patch [1] hasn't landed yet. It really ought to. [1] https://lore.kernel.org/lkml/20181012213926.253765-1-dianders@chromium.org/T/#u Changes in v2: None Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 8cf59452c6756..e2460b666ae45 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -47,6 +47,8 @@ Optional properties: -lanes-per-direction : number of lanes available per direction - either 1 or 2. Note that it is assume same number of lanes is used both directions at once. If not specified, default is 2 lanes per direction. +- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose + PHY reset from the UFS controller. - resets : reset node register - reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP. @@ -76,4 +78,5 @@ Example: reset-names = "rst"; phys = <&ufsphy1>; phy-names = "ufsphy"; + #reset-cells = <1>; }; From patchwork Wed Jan 23 22:11:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1030212 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="kslQlDMz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43lKJm6HV4z9sD4 for ; Thu, 24 Jan 2019 09:12:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726693AbfAWWMH (ORCPT ); Wed, 23 Jan 2019 17:12:07 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:42309 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726366AbfAWWMH (ORCPT ); Wed, 23 Jan 2019 17:12:07 -0500 Received: by mail-pg1-f195.google.com with SMTP id d72so1693718pga.9 for ; Wed, 23 Jan 2019 14:12:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nwEgonuYSGrKbJYDl4G3bbQHZLlfkk1X5XVhYfW28I8=; b=kslQlDMzIjeV/wdofyuFSig3T4gbiRun22xL6zxuqH+/BQjKZvrgfjxEn+BLqR9ig8 WYqmdGl/MPAZzd8WaYhwwaCyR/xpkW/JrqgN+V4HGB965QxnhMrrkVo/DEKuCs7i/kJn h7FwTVDIYPl2/dF3aSbp/sHUksrRYcV1VZixM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nwEgonuYSGrKbJYDl4G3bbQHZLlfkk1X5XVhYfW28I8=; b=AnLZZW0jhf/vmboggVvBT6A8Edmo2A3gx45MoSiY/QEgO2/K5eCYQR/Lh3BMIiVebK J4UpcXsm+uVhmFJs9GDdVBmKdJHhLEa+TKgyCfi+4ySPgvCOnKKnfNnl4ucfg5zWVG/q +krWP9vcVshFS6MJTsodbpYJu4x59i7ff1HAWlDWyaho6s6OYF8BrlgQgKRK6nbRKEAT WwgTsDmhEOkKsYmiHXfRhQxK1C3U1MUh4kYkjUyK8+ckvIojlUHFSHvOEl16oYaWG+KH LRY9BxO9Q9EsmoTjXI4sE5C0J124jhX3TJq3YGBJgPD9bwoYDKBtxbz2lxf+yxgZenQX YEVw== X-Gm-Message-State: AJcUukdiLs89C5PjvC0t7dZqTpFERlPFPFptnoMuHeyQmWMK+HqFgjCt j7GPsky0Qum1NQCsBcC857cWWQ== X-Google-Smtp-Source: ALg8bN5U/FBBt+r8Hj97ySEDpETRZckbgmxnT0QvxqbXfa2sJKmXKP5MrMwojRLrLRJMvAOEghniDg== X-Received: by 2002:a62:104a:: with SMTP id y71mr3798578pfi.34.1548281526447; Wed, 23 Jan 2019 14:12:06 -0800 (PST) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id d18sm27927943pfj.47.2019.01.23.14.12.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 23 Jan 2019 14:12:05 -0800 (PST) From: Evan Green To: Andy Gross , Rob Herring , Kishon Vijay Abraham I Cc: Can Guo , Douglas Anderson , Asutosh Das , Stephen Boyd , Vivek Gautam , Evan Green , devicetree@vger.kernel.org, Mark Rutland , linux-kernel@vger.kernel.org Subject: [PATCH v2 2/9] dt-bindings: phy-qcom-qmp: Add UFS PHY reset Date: Wed, 23 Jan 2019 14:11:30 -0800 Message-Id: <20190123221137.41722-3-evgreen@chromium.org> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20190123221137.41722-1-evgreen@chromium.org> References: <20190123221137.41722-1-evgreen@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a required reset to the SDM845 UFS phy to express the PHY reset bit inside the UFS controller register space. Before this change, this reset was not expressed in the DT, and the driver utilized two different callbacks (phy_init and phy_poweron) to implement a two-phase initialization procedure that involved deasserting this reset between init and poweron. This abused the two callbacks and diluted their purpose. That scheme does not work as regulators cannot be turned off in phy_poweroff because they were turned on in init, rather than poweron. The net result is that regulators are left on in suspend that shouldn't be. This new scheme gives the UFS reset to the PHY, so that it can fully initialize itself in a single callback. We can then turn regulators on during poweron and off during poweroff. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- I realize I'm not supposed to add a required property after the fact, but given that the UFS DT nodes that would use this binding are not yet upstream (and this would be the first), I was hoping to squeak by. Changes in v2: None Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 4ff26dbf43106..49b8a5eed3cd1 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -56,7 +56,8 @@ Required properties: one for each entry in reset-names. - reset-names: "phy" for reset of phy block, "common" for phy common block reset, - "cfg" for phy's ahb cfg block reset. + "cfg" for phy's ahb cfg block reset, + "ufsphy" for the PHY reset in the UFS controller. For "qcom,ipq8074-qmp-pcie-phy" must contain: "phy", "common". @@ -70,7 +71,8 @@ Required properties: "phy", "common". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: "phy", "common". - For "qcom,sdm845-qmp-ufs-phy": no resets are listed. + For "qcom,sdm845-qmp-ufs-phy": must contain: + "ufsphy". - vdda-phy-supply: Phandle to a regulator supply to PHY core block. - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. From patchwork Wed Jan 23 22:11:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1030213 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="NPRbm7pI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43lKKb4Yq0z9s3l for ; Thu, 24 Jan 2019 09:12:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726693AbfAWWMu (ORCPT ); Wed, 23 Jan 2019 17:12:50 -0500 Received: from mail-pf1-f194.google.com ([209.85.210.194]:40881 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726820AbfAWWMK (ORCPT ); Wed, 23 Jan 2019 17:12:10 -0500 Received: by mail-pf1-f194.google.com with SMTP id i12so1875761pfo.7 for ; Wed, 23 Jan 2019 14:12:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mnJ9pOfeoLrRRmLw97XaiwPeSNBQRApiw6Xy7Dc0LLg=; b=NPRbm7pISFFHGvIToej044RIAiArthXEdYhkcetMulujC9H3ASl/+on/hj25jV+GsK nJcfntPb9r6g57TUWCZCI9uRJDcg9S9ClCTMUYuShZ0NTqI92pDytsYQgkWiMFqDPBwB TThXu58/zHO9sveoZZj4mu/aRT3aWHCV+S88E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mnJ9pOfeoLrRRmLw97XaiwPeSNBQRApiw6Xy7Dc0LLg=; b=ecH6JJ9av2/u0QNZ8piMF2gzNcr5dBlCdpFpQTi4FTFFGZJF8MOU5y+zK6zhcVJnf/ bYrQYmp+v6USpUV9hqTbhx/OdUSm0+pNPt3zm/nK4UWUDClE4VWZaTz1sMpRkMM3gbsv V7EDAraQZfq1Pyq2nqvi9iEupQD11OVMthbu3QfMcXK7uwhUcR7vKbNUv4wKWFbwVfMc L4hCKb/EdY4QOBNnN9Hh7JEQUaDGvZ54kfVq5bcOQSJh6xl+UnDzkey0mtc8khKD5Jsw 5feIhwqhaL5qUYl4+Ivs3UZUNiTvKsBJQGRdEvQBqBNbfx/gRmGJd7jbzpA8sJtCn9Z2 nsxA== X-Gm-Message-State: AJcUukdPGdmTn81Ny8P+7h3PN0h9n/DIh7hit5PvlM1Z7DRaeL8fA3di iNplorChj8YSXHRxgjANilQ8Pg== X-Google-Smtp-Source: ALg8bN6dq4y1P6J9DWWTH1fls/a2uIL4FiXEP0+jWadWvkIrwOOTX7+8GFOY+r0FTqwUE/a6YNWBVg== X-Received: by 2002:a63:b649:: with SMTP id v9mr3645160pgt.436.1548281529187; Wed, 23 Jan 2019 14:12:09 -0800 (PST) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id d18sm27927943pfj.47.2019.01.23.14.12.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 23 Jan 2019 14:12:08 -0800 (PST) From: Evan Green To: Andy Gross , Rob Herring , Kishon Vijay Abraham I Cc: Can Guo , Douglas Anderson , Asutosh Das , Stephen Boyd , Vivek Gautam , Evan Green , devicetree@vger.kernel.org, Mark Rutland , linux-kernel@vger.kernel.org Subject: [PATCH v2 3/9] dt-bindings: phy: qcom-ufs: Add resets property Date: Wed, 23 Jan 2019 14:11:31 -0800 Message-Id: <20190123221137.41722-4-evgreen@chromium.org> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20190123221137.41722-1-evgreen@chromium.org> References: <20190123221137.41722-1-evgreen@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a resets property to the PHY that represents the PHY reset register in the UFS controller itself. This better describes the complete specification of the PHY, and allows the PHY to perform its initialization in a single function, rather than relying on back-channel sequencing of initialization through the PHY framework. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- Changes in v2: - Added resets to example (Stephen). Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt index 21d9a93db2e97..fd59f93e95562 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt @@ -29,6 +29,7 @@ Optional properties: - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply +- resets : specifies the PHY reset in the UFS controller Example: @@ -51,9 +52,11 @@ Example: <&clock_gcc clk_ufs_phy_ldo>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; + resets = <&ufshc 0>; }; - ufshc@fc598000 { + ufshc: ufshc@fc598000 { + #reset-cells = <1>; ... phys = <&ufsphy1>; phy-names = "ufsphy";