From patchwork Tue Jan 8 09:58:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1021822 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43Ynn802WVz9sMQ for ; Tue, 8 Jan 2019 21:00:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43Ynn75hq3zDqSS for ; Tue, 8 Jan 2019 21:00:11 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43YnmH6rTvzDqSf for ; Tue, 8 Jan 2019 20:59:27 +1100 (AEDT) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x089x7jZ180948 for ; Tue, 8 Jan 2019 04:59:25 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 2pvr7jd5sn-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 04:59:25 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 8 Jan 2019 09:59:23 -0000 Received: from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194) by e06smtp04.uk.ibm.com (192.168.101.134) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 8 Jan 2019 09:59:22 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x089xKAI12648688 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Jan 2019 09:59:20 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2CC28AE04D; Tue, 8 Jan 2019 09:59:20 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2F0DCAE051; Tue, 8 Jan 2019 09:59:18 +0000 (GMT) Received: from vajain21.in.ibm.com (unknown [9.109.223.28]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 8 Jan 2019 09:59:18 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith , Vasant Hegde Date: Tue, 8 Jan 2019 15:28:55 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190108095902.24718-1-vaibhav@linux.ibm.com> References: <20190108095902.24718-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19010809-0016-0000-0000-00000241DE1A X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010809-0017-0000-0000-0000329BF0C9 Message-Id: <20190108095902.24718-2-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-08_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901080082 Subject: [Skiboot] [PATCH v3 1/8] opal: Update opal_del_host_sync_notifier() to accept 'void *data' X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Current implementation of opal_del_host_sync_notifier() will only delete the first entry of the 'notify' callback found from opal_syncers list irrespective of the 'data' of list-node. This is problematic when multiple notifiers with same callback function but different 'data' are registered. In this case when the cleanup code will call opal_del_host_sync_notifier() it cannot be sure if correct opal_syncer is removed. Hence this patch updates the function to accept a new argument named 'void *data' which is then used to iterates over the opal_syncers list and only remove the first node node having the matching value for 'notify' callback as 'data'. Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard Reviewed-by: Vasant Hegde Signed-off-by: Vaibhav Jain Reviewed-by: Frederic Barrat --- Change-log v3: None/Respining the patchset v2: Instead of introducing a new function, update the existing function opal_del_host_sync_notifier() to accept 'void *data' [Vasant] --- core/opal.c | 7 +++++-- include/opal-internal.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/core/opal.c b/core/opal.c index 3a8ea30b..87aca61c 100644 --- a/core/opal.c +++ b/core/opal.c @@ -683,12 +683,15 @@ void opal_add_host_sync_notifier(bool (*notify)(void *data), void *data) list_add_tail(&opal_syncers, &ent->link); } -void opal_del_host_sync_notifier(bool (*notify)(void *data)) +/* + * Remove a host sync notifier for given callback and data + */ +void opal_del_host_sync_notifier(bool (*notify)(void *data), void *data) { struct opal_sync_entry *ent; list_for_each(&opal_syncers, ent, link) { - if (ent->notify == notify) { + if (ent->notify == notify && ent->data == data) { list_del(&ent->link); free(ent); return; diff --git a/include/opal-internal.h b/include/opal-internal.h index 40bad457..2ce25adb 100644 --- a/include/opal-internal.h +++ b/include/opal-internal.h @@ -76,7 +76,7 @@ extern void opal_run_pollers(void); * Warning: no locking, only call that from the init processor */ extern void opal_add_host_sync_notifier(bool (*notify)(void *data), void *data); -extern void opal_del_host_sync_notifier(bool (*notify)(void *data)); +extern void opal_del_host_sync_notifier(bool (*notify)(void *data), void *data); /* * Opal internal function prototype From patchwork Tue Jan 8 09:58:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1021823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43YnnN6hQMz9sMp for ; Tue, 8 Jan 2019 21:00:24 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43YnnN3WvpzDqRk for ; Tue, 8 Jan 2019 21:00:24 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43YnmN65tSzDqRc for ; Tue, 8 Jan 2019 20:59:32 +1100 (AEDT) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x089x9J5044233 for ; Tue, 8 Jan 2019 04:59:30 -0500 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pvr32nxvd-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 04:59:30 -0500 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 8 Jan 2019 09:59:28 -0000 Received: from b06cxnps3075.portsmouth.uk.ibm.com (9.149.109.195) by e06smtp07.uk.ibm.com (192.168.101.137) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 8 Jan 2019 09:59:25 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x089xNav50724952 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Jan 2019 09:59:23 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6FF87AE053; Tue, 8 Jan 2019 09:59:23 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9C5EDAE051; Tue, 8 Jan 2019 09:59:21 +0000 (GMT) Received: from vajain21.in.ibm.com (unknown [9.109.223.28]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 8 Jan 2019 09:59:21 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith , Vasant Hegde Date: Tue, 8 Jan 2019 15:28:56 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190108095902.24718-1-vaibhav@linux.ibm.com> References: <20190108095902.24718-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19010809-0028-0000-0000-00000335DAAF X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010809-0029-0000-0000-000023F2E73D Message-Id: <20190108095902.24718-3-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-08_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901080082 Subject: [Skiboot] [PATCH v3 2/8] core/pci: Introduce a new pci_slot_op named completed_sm_run() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" At times we need to perform some cleanup activities when the Opal PCI state machine that perform creset/freset/hreset (driven by pci_slot_ops->run_sm which) of a slot completes. One example can be to mark CAPP attached to a PHB, as deactivated when creset/freset of a CAPI card slot is completed. However the calls to pci_slot_ops->run_sm() is scattered through out the code and patching each call site to check for the return value and perform custom cleanup tacks is difficult. Hence this patch introduces a new pci_slot_ops named completed_sm_run() which should be called when pci_slot_ops->run_sm() determines that the reset state machine is complete. This provides a more centralized way to handle slot related cleanup activities. Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard Signed-off-by: Vaibhav Jain Reviewed-by: Frederic Barrat --- Change-log v3: None. Respinning the patchset v2: Update the callback signature to return a int64_t back to caller. [Andrew] --- core/pci-slot.c | 6 +++++- include/pci-slot.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/core/pci-slot.c b/core/pci-slot.c index 71d2769e..497d0a47 100644 --- a/core/pci-slot.c +++ b/core/pci-slot.c @@ -104,9 +104,13 @@ static int64_t pci_slot_run_sm(struct pci_slot *slot) prlog(PR_ERR, PCI_SLOT_PREFIX "Invalid state %08x\n", slot->id, slot->state); pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); - return OPAL_HARDWARE; + ret = OPAL_HARDWARE; } + /* Notify about the pci slot state machine completion */ + if (ret <= 0 && slot->ops.completed_sm_run) + slot->ops.completed_sm_run(slot, ret); + return ret; } diff --git a/include/pci-slot.h b/include/pci-slot.h index cd757535..708374b6 100644 --- a/include/pci-slot.h +++ b/include/pci-slot.h @@ -110,6 +110,7 @@ struct pci_slot_ops { int64_t (*freset)(struct pci_slot *slot); int64_t (*hreset)(struct pci_slot *slot); int64_t (*run_sm)(struct pci_slot *slot); + int64_t (*completed_sm_run)(struct pci_slot *slot, uint64_t err); /* Auxillary functions */ void (*add_properties)(struct pci_slot *slot, struct dt_node *np); From patchwork Tue Jan 8 09:58:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1021824 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43Ynnp3y4vz9sMQ for ; Tue, 8 Jan 2019 21:00:46 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43Ynnp0kZzzDq5x for ; Tue, 8 Jan 2019 21:00:46 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43YnmR4DdqzDqRk for ; Tue, 8 Jan 2019 20:59:35 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x089x85f037473 for ; Tue, 8 Jan 2019 04:59:32 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0b-001b2d01.pphosted.com with ESMTP id 2pvrs7befu-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 04:59:32 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 8 Jan 2019 09:59:31 -0000 Received: from b06cxnps4075.portsmouth.uk.ibm.com (9.149.109.197) by e06smtp02.uk.ibm.com (192.168.101.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 8 Jan 2019 09:59:28 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x089xQeD64749738 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Jan 2019 09:59:26 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 77716AE051; Tue, 8 Jan 2019 09:59:26 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BCEB4AE053; Tue, 8 Jan 2019 09:59:24 +0000 (GMT) Received: from vajain21.in.ibm.com (unknown [9.109.223.28]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 8 Jan 2019 09:59:24 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith , Vasant Hegde Date: Tue, 8 Jan 2019 15:28:57 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190108095902.24718-1-vaibhav@linux.ibm.com> References: <20190108095902.24718-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19010809-0008-0000-0000-000002ACD1C8 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010809-0009-0000-0000-00002218DF14 Message-Id: <20190108095902.24718-4-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-08_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901080082 Subject: [Skiboot] [PATCH v3 3/8] capp/phb: Introduce 'struct capp' to hold capp related info in 'struct phb' X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Previously struct proc_chip member 'capp_phb3_attached_mask' was used for Power-8 to keep track of PHB attached to the single CAPP on the chip. CAPP on that chip supported a flexible PHB assignment scheme. However since then new chips only support a static assignment i.e a CAPP can only be attached to a specific PEC. Hence instead of using 'proc_chip.capp_phb4_attached_mask' to manage CAPP <-> PEC assignments which needs a global lock (capi_lock) to be updated, we introduce a new struct named 'capp' a pointer to which resides inside struct 'phb4'. Since updates to struct 'phb4' already happen in context of phb_lock; this eliminates the need to use mutex 'capi_lock' while updating 'capp_phb4_attached_mask'. This struct is also used to hold CAPP specific variables such as pointer to the 'struct phb' to which the CAPP is attached, 'capp_xscom_offset' which is the xscom offset to be added to CAPP registers in case there are more than 1 on the chip, 'capp_index' which is the index of the CAPP on the chip, and attached_pe' which is the process endpoint index to which CAPP is attached. Finally member 'chip_id' holds the chip-id thats used for performing xscom read/writes. Also new helpers named capp_xscom_read()/write() are introduced to make access to CAPP xscom registers easier. Signed-off-by: Vaibhav Jain Reviewed-by: Christophe Lombard Reviewed-by: Andrew Donnellan --- Change-log v3: Moved the 'struct capp *' from struct 'phb' to struct 'phb4' [ Christophe ] Introduced 'chip_id' as a member of struct 'capp'. Introduced helpers capp_xscom_read()/write(). --- hw/capp.c | 12 ++++++++++++ hw/phb4.c | 52 +++++++++++++++++++++++++++++++++++++++++++------- include/capp.h | 12 ++++++++++++ include/chip.h | 1 - include/phb4.h | 3 +++ 5 files changed, 72 insertions(+), 8 deletions(-) diff --git a/hw/capp.c b/hw/capp.c index eeaa4ac4..b3984ea0 100644 --- a/hw/capp.c +++ b/hw/capp.c @@ -240,3 +240,15 @@ int64_t capp_get_info(int chip_id, struct phb *phb, struct capp_info *info) return OPAL_PARAMETER; } + +int64_t capp_xscom_read(struct capp *capp, int64_t off, uint64_t *val) +{ + return capp == NULL ? OPAL_UNSUPPORTED : + xscom_read(capp->chip_id, off + capp->capp_xscom_offset, val); +} + +int64_t capp_xscom_write(struct capp *capp, int64_t off, uint64_t val) +{ + return capp == NULL ? OPAL_UNSUPPORTED : + xscom_write(capp->chip_id, off + capp->capp_xscom_offset, val); +} diff --git a/hw/phb4.c b/hw/phb4.c index c0797647..59a96680 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3880,13 +3880,13 @@ static int64_t phb4_get_capp_info(int chip_id, struct phb *phb, struct capp_info *info) { struct phb4 *p = phb_to_phb4(phb); - struct proc_chip *chip = get_chip(p->chip_id); uint32_t offset; if (chip_id != p->chip_id) return OPAL_PARAMETER; - if (!((1 << p->index) & chip->capp_phb4_attached_mask)) + /* Check is CAPP is attached to the PHB */ + if (p->capp == NULL || p->capp->phb != phb) return OPAL_PARAMETER; offset = PHB4_CAPP_REG_OFFSET(p); @@ -4397,23 +4397,61 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, return OPAL_SUCCESS; } + +static int64_t phb4_init_capp(struct phb4 *p) +{ + struct capp *capp; + int rc; + + if (p->index != CAPP0_PHB_INDEX && + p->index != CAPP1_PHB_INDEX) + return OPAL_UNSUPPORTED; + + capp = zalloc(sizeof(struct capp)); + if (capp == NULL) + return OPAL_NO_MEM; + + if (p->index == CAPP0_PHB_INDEX) { + capp->capp_index = 0; + capp->capp_xscom_offset = 0; + + } else if (p->index == CAPP1_PHB_INDEX) { + capp->capp_index = 1; + capp->capp_xscom_offset = CAPP1_REG_OFFSET; + } + + capp->attached_pe = phb4_get_reserved_pe_number(&p->phb); + capp->chip_id = p->chip_id; + + /* Load capp microcode into the capp unit */ + rc = load_capp_ucode(p); + + if (rc == OPAL_SUCCESS) + p->capp = capp; + + return rc; +} + static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, uint64_t pe_number) { struct phb4 *p = phb_to_phb4(phb); struct proc_chip *chip = get_chip(p->chip_id); + struct capp *capp = p->capp; uint64_t reg, ret; uint32_t offset; + if (capp == NULL) + return OPAL_UNSUPPORTED; if (!capp_ucode_loaded(chip, p->index)) { PHBERR(p, "CAPP: ucode not loaded\n"); return OPAL_RESOURCE; } - lock(&capi_lock); - chip->capp_phb4_attached_mask |= 1 << p->index; - unlock(&capi_lock); + /* mark the capp attached to the phb */ + capp->phb = phb; + capp->attached_pe = pe_number; offset = PHB4_CAPP_REG_OFFSET(p); xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®); @@ -5595,8 +5633,8 @@ static void phb4_create(struct dt_node *np) /* Get the HW up and running */ phb4_init_hw(p); - /* Load capp microcode into capp unit */ - load_capp_ucode(p); + /* init capp that might get attached to the phb */ + phb4_init_capp(p); /* Compute XIVE source flags depending on PHB revision */ irq_flags = 0; diff --git a/include/capp.h b/include/capp.h index 6ec3f7fe..cc70e443 100644 --- a/include/capp.h +++ b/include/capp.h @@ -79,6 +79,14 @@ struct capp_ops { int64_t (*get_capp_info)(int, struct phb *, struct capp_info *); }; +struct capp { + struct phb *phb; + unsigned int capp_index; + uint64_t capp_xscom_offset; + uint64_t attached_pe; + uint64_t chip_id; +}; + struct proc_chip; extern struct lock capi_lock; extern struct capp_ops capi_ops; @@ -96,4 +104,8 @@ extern int64_t capp_load_ucode(unsigned int chip_id, uint32_t opal_id, extern int64_t capp_get_info(int chip_id, struct phb *phb, struct capp_info *info); + +/* Helpers to read/write capp registers */ +extern int64_t capp_xscom_read(struct capp *capp, int64_t off, uint64_t *val); +extern int64_t capp_xscom_write(struct capp *capp, int64_t off, uint64_t val); #endif /* __CAPP_H */ diff --git a/include/chip.h b/include/chip.h index 2fb8126d..c759d0a0 100644 --- a/include/chip.h +++ b/include/chip.h @@ -197,7 +197,6 @@ struct proc_chip { /* Must hold capi_lock to change */ uint8_t capp_phb3_attached_mask; - uint8_t capp_phb4_attached_mask; uint8_t capp_ucode_loaded; /* Used by hw/centaur.c */ diff --git a/include/phb4.h b/include/phb4.h index 43819d57..60c1735d 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -232,6 +232,9 @@ struct phb4 { /* Current NPU2 relaxed ordering state */ bool ro_state; + /* Any capp instance attached to the PHB4 */ + struct capp *capp; + struct phb phb; }; From patchwork Tue Jan 8 09:58:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1021825 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43Ynp973Kmz9sDr for ; Tue, 8 Jan 2019 21:01:05 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43Ynp95sQLzDqSJ for ; Tue, 8 Jan 2019 21:01:05 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43YnmW1ZnTzDqPS for ; Tue, 8 Jan 2019 20:59:39 +1100 (AEDT) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x089x6ql128635 for ; Tue, 8 Jan 2019 04:59:36 -0500 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pvrqp3n81-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 04:59:36 -0500 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 8 Jan 2019 09:59:34 -0000 Received: from b06cxnps4074.portsmouth.uk.ibm.com (9.149.109.196) by e06smtp07.uk.ibm.com (192.168.101.137) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 8 Jan 2019 09:59:31 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x089xThr9765278 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Jan 2019 09:59:29 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 74A47AE053; Tue, 8 Jan 2019 09:59:29 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C40DDAE04D; Tue, 8 Jan 2019 09:59:27 +0000 (GMT) Received: from vajain21.in.ibm.com (unknown [9.109.223.28]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 8 Jan 2019 09:59:27 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith , Vasant Hegde Date: Tue, 8 Jan 2019 15:28:58 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190108095902.24718-1-vaibhav@linux.ibm.com> References: <20190108095902.24718-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19010809-0028-0000-0000-00000335DAB4 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010809-0029-0000-0000-000023F2E742 Message-Id: <20190108095902.24718-5-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-08_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901080082 Subject: [Skiboot] [PATCH v3 4/8] phb4/capp: Update and re-factor phb4_set_capi_mode() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Presently phb4_set_capi_mode() performs certain CAPP checks like, checking of CAPP ucode loaded or checks if CAPP is still in recovery, even when the requested mode is to switch to PCI mode. Hence this patch updates and re-factors phb4_set_capi_mode() to make sure CAPP related checks are only performed when request to enable CAPP is made by mode==OPAL_PHB_CAPI_MODE_CAPI/DMA_TVT1. We also update other possible modes requests to return a more appropriate status code based on if CAPP is activated or not. Signed-off-by: Vaibhav Jain Reviewed-by: Christophe Lombard Reviewed-by: Andrew Donnellan --- Change-log v3: Updated the code to use capp_xscom_read() instead of xscom_read(). Moved the check for CAPP recovery in progress from MODE_CAPI/DMA to all CAPP mode switch requests. This preserves existing behaviour expected by CX5 driver. [ Christophe ] Fixed a minor spelling. [ Andrew ] v2: Using 'struct capp* instead of global 'capi_lock' to indicate that CAPP is now attached to a PHB [Andrew] Code formatting that removed the use of a confusing tertiary operator. [Andrew] --- hw/phb4.c | 88 +++++++++++++++++++++++++++++++++---------------------- 1 file changed, 53 insertions(+), 35 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 59a96680..eba9ae3f 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -4439,54 +4439,72 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, struct proc_chip *chip = get_chip(p->chip_id); struct capp *capp = p->capp; uint64_t reg, ret; - uint32_t offset; - - if (capp == NULL) - return OPAL_UNSUPPORTED; - if (!capp_ucode_loaded(chip, p->index)) { - PHBERR(p, "CAPP: ucode not loaded\n"); - return OPAL_RESOURCE; - } - - /* mark the capp attached to the phb */ - capp->phb = phb; - capp->attached_pe = pe_number; + /* cant do a mode switch when capp is in recovery mode */ + ret = capp_xscom_read(capp, CAPP_ERR_STATUS_CTRL, ®); + if (ret != OPAL_SUCCESS) + return ret; - offset = PHB4_CAPP_REG_OFFSET(p); - xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®); - if ((reg & PPC_BIT(5))) { - PHBERR(p, "CAPP: recovery failed (%016llx)\n", reg); - return OPAL_HARDWARE; - } else if ((reg & PPC_BIT(0)) && (!(reg & PPC_BIT(1)))) { + if ((reg & PPC_BIT(0)) && (!(reg & PPC_BIT(1)))) { PHBDBG(p, "CAPP: recovery in progress\n"); return OPAL_BUSY; } + switch (mode) { - case OPAL_PHB_CAPI_MODE_CAPI: - ret = enable_capi_mode(p, pe_number, - CAPP_MAX_STQ_ENGINES | - CAPP_MIN_DMA_READ_ENGINES); - disable_fast_reboot("CAPP being enabled"); + + case OPAL_PHB_CAPI_MODE_DMA: /* Enabled by default on p9 */ + case OPAL_PHB_CAPI_MODE_SNOOP_ON: + /* nothing to do on P9 if CAPP is already enabled */ + ret = p->capp->phb ? OPAL_SUCCESS : OPAL_UNSUPPORTED; break; - case OPAL_PHB_CAPI_MODE_DMA_TVT1: - ret = enable_capi_mode(p, pe_number, - CAPP_MIN_STQ_ENGINES | - CAPP_MAX_DMA_READ_ENGINES); - disable_fast_reboot("CAPP being enabled"); + + case OPAL_PHB_CAPI_MODE_SNOOP_OFF: + case OPAL_PHB_CAPI_MODE_PCIE: /* Not supported at the moment */ + ret = p->capp->phb ? OPAL_UNSUPPORTED : OPAL_SUCCESS; break; - case OPAL_PHB_CAPI_MODE_SNOOP_ON: - /* nothing to do P9 if CAPP is alreay enabled */ - ret = OPAL_SUCCESS; + + case OPAL_PHB_CAPI_MODE_CAPI: /* Fall Through */ + case OPAL_PHB_CAPI_MODE_DMA_TVT1: + /* Check if ucode is available */ + if (!capp_ucode_loaded(chip, p->index)) { + PHBERR(p, "CAPP: ucode not loaded\n"); + ret = OPAL_RESOURCE; + break; + } + + /* + * Mark the CAPP attached to the PHB right away so that + * if a MCE happens during CAPP init we can handle it. + * In case of an error in CAPP init we remove the PHB + * from the attached_mask later. + */ + capp->phb = phb; + capp->attached_pe = pe_number; + + if (mode == OPAL_PHB_CAPI_MODE_DMA_TVT1) + ret = enable_capi_mode(p, pe_number, + CAPP_MIN_STQ_ENGINES | + CAPP_MAX_DMA_READ_ENGINES); + + else + ret = enable_capi_mode(p, pe_number, + CAPP_MAX_STQ_ENGINES | + CAPP_MIN_DMA_READ_ENGINES); + if (ret == OPAL_SUCCESS) { + /* Disable fast reboot for CAPP */ + disable_fast_reboot("CAPP being enabled"); + } else { + /* In case of an error mark the PHB detached */ + capp->phb = NULL; + capp->attached_pe = phb4_get_reserved_pe_number(phb); + } break; - case OPAL_PHB_CAPI_MODE_PCIE: /* shouldn't be called on p9*/ - case OPAL_PHB_CAPI_MODE_DMA: /* Enabled by default on p9 */ - case OPAL_PHB_CAPI_MODE_SNOOP_OFF: /* shouldn't be called on p9*/ default: ret = OPAL_UNSUPPORTED; - } + break; + }; return ret; } From patchwork Tue Jan 8 09:58:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1021826 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43YnpR2nTLz9sDr for ; Tue, 8 Jan 2019 21:01:19 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43YnpR1L72zDqSl for ; Tue, 8 Jan 2019 21:01:19 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43YnmX552RzDqS7 for ; Tue, 8 Jan 2019 20:59:40 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x089x96N120932 for ; Tue, 8 Jan 2019 04:59:38 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pvpcmtxdk-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 04:59:38 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 8 Jan 2019 09:59:36 -0000 Received: from b06cxnps4076.portsmouth.uk.ibm.com (9.149.109.198) by e06smtp04.uk.ibm.com (192.168.101.134) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 8 Jan 2019 09:59:34 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x089xWUj65994826 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Jan 2019 09:59:32 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 61C72AE051; Tue, 8 Jan 2019 09:59:32 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CB663AE045; Tue, 8 Jan 2019 09:59:30 +0000 (GMT) Received: from vajain21.in.ibm.com (unknown [9.109.223.28]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 8 Jan 2019 09:59:30 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith , Vasant Hegde Date: Tue, 8 Jan 2019 15:28:59 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190108095902.24718-1-vaibhav@linux.ibm.com> References: <20190108095902.24718-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19010809-0016-0000-0000-00000241DE24 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010809-0017-0000-0000-0000329BF0D2 Message-Id: <20190108095902.24718-6-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-08_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901080082 Subject: [Skiboot] [PATCH v3 5/8] capp/phb4: Force CAPP to PCIe mode during kernel shutdown X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch introduces a new opal syncer for PHB4 named phb4_host_sync_reset(). We register this opal syncer when CAPP is activated successfully in phb4_set_capi_mode() so that it will be called at kernel shutdown during fast-reset. During kernel shutdown the function will then repeatedly call phb->ops->set_capi_mode() to switch switch CAPP to PCIe mode. In case set_capi_mode() indicates its OPAL_BUSY, which indicates that CAPP is still transitioning to new state; it calls slot->ops.run_sm() to ensure that Opal slot reset state machine makes forward progress. Signed-off-by: Vaibhav Jain Reviewed-by: Christophe Lombard Reviewed-by: Andrew Donnellan Reviewed-by: Frederic Barrat --- Change-log v3: Updated code to use struct phb4->capp instead of struct phb->capp. --- hw/phb4.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/hw/phb4.c b/hw/phb4.c index eba9ae3f..229617c5 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2768,6 +2768,37 @@ static void phb4_training_trace(struct phb4 *p) } } +/* + * This helper is called repeatedly by the host sync notifier mechanism, which + * relies on the kernel to regularly poll the OPAL_SYNC_HOST_REBOOT call as it + * shuts down. + */ +static bool phb4_host_sync_reset(void *data) +{ + struct phb4 *p = (struct phb4 *)data; + struct phb *phb = &p->phb; + int64_t rc = 0; + + /* Make sure no-one modifies the phb flags while we are active */ + phb_lock(phb); + + /* Make sure CAPP is attached to the PHB */ + if (p->capp) + /* Call phb ops to disable capi */ + rc = phb->ops->set_capi_mode(phb, OPAL_PHB_CAPI_MODE_PCIE, + p->capp->attached_pe); + else + rc = OPAL_SUCCESS; + + /* Continue kicking state-machine if in middle of a mode transition */ + if (rc == OPAL_BUSY) + rc = phb->slot->ops.run_sm(phb->slot); + + phb_unlock(phb); + + return rc <= OPAL_SUCCESS; +} + static int64_t phb4_poll_link(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); @@ -4492,6 +4523,9 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, CAPP_MAX_STQ_ENGINES | CAPP_MIN_DMA_READ_ENGINES); if (ret == OPAL_SUCCESS) { + /* register notification on system shutdown */ + opal_add_host_sync_notifier(&phb4_host_sync_reset, p); + /* Disable fast reboot for CAPP */ disable_fast_reboot("CAPP being enabled"); } else { From patchwork Tue Jan 8 09:59:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1021827 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43Ynpj3ljNz9sDr for ; Tue, 8 Jan 2019 21:01:33 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43Ynpj2gFgzDqRk for ; Tue, 8 Jan 2019 21:01:33 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43Ynmc2QmSzDqSD for ; Tue, 8 Jan 2019 20:59:44 +1100 (AEDT) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x089x5Z9024848 for ; Tue, 8 Jan 2019 04:59:42 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pvsd016bs-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 04:59:42 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 8 Jan 2019 09:59:39 -0000 Received: from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194) by e06smtp05.uk.ibm.com (192.168.101.135) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 8 Jan 2019 09:59:37 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x089xZ2X60948612 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Jan 2019 09:59:35 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9C5F8AE057; Tue, 8 Jan 2019 09:59:35 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B90FDAE045; Tue, 8 Jan 2019 09:59:33 +0000 (GMT) Received: from vajain21.in.ibm.com (unknown [9.109.223.28]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 8 Jan 2019 09:59:33 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith , Vasant Hegde Date: Tue, 8 Jan 2019 15:29:00 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190108095902.24718-1-vaibhav@linux.ibm.com> References: <20190108095902.24718-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19010809-0020-0000-0000-00000302E166 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010809-0021-0000-0000-00002153F1BF Message-Id: <20190108095902.24718-7-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-08_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901080082 Subject: [Skiboot] [PATCH v3 6/8] capp/phb4: Introduce PHB4 flag, PHB4_CAPP_DISABLE to disable CAPP X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch introduces a PHB4 flag PHB4_CAPP_DISABLE and scaffolding necessary to handle it during CRESET flow. The flag is set when CAPP is request to switch to PCIe mode via call to phb4_set_capi_mode() with mode OPAL_PHB_CAPI_MODE_PCIE. This starts the below sequence that ultimately ends in newly introduced phb4_slot_sm_run_completed() 1. Set PHB4_CAPP_DISABLE to phb4->flags. 2. Start a CRESET on the phb slot. This also starts the opal pci reset state machine. 3. Wait for slot state to be PHB4_SLOT_CRESET_WAIT_CQ. 4. Perform CAPP recovery as PHB is still fenced, by calling do_capp_recovery_scoms(). 5. Call newly introduced 'disable_capi_mode()' to disable CAPP. 6. Wait for slot reset to complete while it transitions to PHB4_SLOT_FRESET and optionally to PHB4_SLOT_LINK_START. 7. Once slot reset is complete opal pci-core state machine will call slot->ops.completed_sm_run(). 8. For PHB4 this branches newly introduced 'phb4_slot_sm_run_completed()'. 9. Inside this function we mark the CAPP as disabled and un-register the opal syncer phb4_host_sync_reset(). 10. Optionally if the slot reset was unsuccessful disable fast-reboot. **************************** Notes: **************************** a. Function 'disable_capi_mode()' performs various sanity tests on CAPP to to determine if its ok to disable it and perform necessary xscoms to disable it. However the current implementation proposed in this patch is a skeleton one that just does sanity tests. A followup patch will be proposed that implements the xscoms necessary to disable CAPP. b. The sequence expects that Opal PCI reset state machine makes forward progress hence needs someone to call slot->ops.run_sm(). This can be either from phb4_host_sync_reset() or opal_pci_poll(). Reviewed-by: Andrew Donnellan Signed-off-by: Vaibhav Jain Reviewed-by: Christophe Lombard Reviewed-by: Frederic Barrat --- Change-log v3: Use 'struct capp *' from struct phb4 instead of struct phb. Minor typo fixed. [ Andrew ] v2: Removed the usage of global mutex 'capi_lock'. [Andrew, Stewart] Populate and use the newly introduced 'struct capp' to maintain the state of capp. --- hw/phb4.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++- include/phb4.h | 1 + 2 files changed, 97 insertions(+), 1 deletion(-) diff --git a/hw/phb4.c b/hw/phb4.c index 229617c5..88b1a6fb 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2799,6 +2799,36 @@ static bool phb4_host_sync_reset(void *data) return rc <= OPAL_SUCCESS; } +/* + * Notification from the pci-core that a pci slot state machine completed. + * We use this callback to mark the CAPP disabled if we were waiting for it. + */ +static int64_t phb4_slot_sm_run_completed(struct pci_slot *slot, uint64_t err) +{ + struct phb4 *p = phb_to_phb4(slot->phb); + + /* Check if we are disabling the capp */ + if (p->flags & PHB4_CAPP_DISABLE) { + + /* Unset struct capp so that we dont fall into a creset loop */ + p->flags &= ~(PHB4_CAPP_DISABLE); + p->capp->phb = NULL; + p->capp->attached_pe = phb4_get_reserved_pe_number(&p->phb); + + /* Remove the host sync notifier is we are done.*/ + opal_del_host_sync_notifier(phb4_host_sync_reset, p); + if (err) { + /* Force a CEC ipl reboot */ + disable_fast_reboot("CAPP: reset failed"); + PHBERR(p, "CAPP: Unable to reset. Error=%lld\n", err); + } else { + PHBINF(p, "CAPP: reset complete\n"); + } + } + + return OPAL_SUCCESS; +} + static int64_t phb4_poll_link(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); @@ -3155,6 +3185,42 @@ static int do_capp_recovery_scoms(struct phb4 *p) return rc; } +/* + * Disable CAPI mode on a PHB. Must be done while PHB is fenced and + * not in recovery. + */ +static void disable_capi_mode(struct phb4 *p) +{ + uint64_t reg; + struct capp *capp = p->capp; + + PHBINF(p, "CAPP: Deactivating\n"); + + /* Check if CAPP attached to the PHB and active */ + if (!capp || capp->phb != &p->phb) { + PHBDBG(p, "CAPP: Not attached to this PHB!\n"); + return; + } + + xscom_read(p->chip_id, p->pe_xscom + XPEC_NEST_CAPP_CNTL, ®); + if (!(reg & PPC_BIT(0))) { + /* Not in CAPI mode, no action required */ + PHBERR(p, "CAPP: Not enabled!\n"); + return; + } + + /* CAPP should already be out of recovery in this function */ + capp_xscom_read(capp, CAPP_ERR_STATUS_CTRL, ®); + if (reg & PPC_BIT(0)) { + PHBERR(p, "CAPP: Can't disable while still in recovery!\n"); + return; + } + + PHBINF(p, "CAPP: Disabling CAPI mode\n"); + + /* Implement procedure to disable CAPP based on h/w sequence */ +} + static int64_t phb4_creset(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); @@ -3215,6 +3281,9 @@ static int64_t phb4_creset(struct pci_slot *slot) (do_capp_recovery_scoms(p) != OPAL_SUCCESS)) goto error; + if (p->flags & PHB4_CAPP_DISABLE) + disable_capi_mode(p); + /* Clear errors in PFIR and NFIR */ xscom_write(p->chip_id, p->pci_stk_xscom + 0x1, ~p->pfir_cache); @@ -3318,6 +3387,7 @@ static struct pci_slot *phb4_slot_create(struct phb *phb) slot->ops.hreset = phb4_hreset; slot->ops.freset = phb4_freset; slot->ops.creset = phb4_creset; + slot->ops.completed_sm_run = phb4_slot_sm_run_completed; slot->link_retries = PHB4_LINK_LINK_RETRIES; return slot; @@ -4491,12 +4561,37 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, break; case OPAL_PHB_CAPI_MODE_SNOOP_OFF: - case OPAL_PHB_CAPI_MODE_PCIE: /* Not supported at the moment */ ret = p->capp->phb ? OPAL_UNSUPPORTED : OPAL_SUCCESS; break; + case OPAL_PHB_CAPI_MODE_PCIE: + if (p->flags & PHB4_CAPP_DISABLE) { + /* We are in middle of a CAPP disable */ + ret = OPAL_BUSY; + + } else if (capp->phb) { + /* Kick start a creset */ + p->flags |= PHB4_CAPP_DISABLE; + PHBINF(p, "CAPP: PCIE mode needs a cold-reset\n"); + /* Kick off the pci state machine */ + ret = phb4_creset(phb->slot); + ret = ret > 0 ? OPAL_BUSY : ret; + + } else { + /* PHB already in PCI mode */ + ret = OPAL_SUCCESS; + } + break; + case OPAL_PHB_CAPI_MODE_CAPI: /* Fall Through */ case OPAL_PHB_CAPI_MODE_DMA_TVT1: + /* Make sure that PHB is not disabling CAPP */ + if (p->flags & PHB4_CAPP_DISABLE) { + PHBERR(p, "CAPP: Disable in progress\n"); + ret = OPAL_BUSY; + break; + } + /* Check if ucode is available */ if (!capp_ucode_loaded(chip, p->index)) { PHBERR(p, "CAPP: ucode not loaded\n"); diff --git a/include/phb4.h b/include/phb4.h index 60c1735d..da3d5d1f 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -166,6 +166,7 @@ struct phb4_err { #define PHB4_CFG_USE_ASB 0x00000002 #define PHB4_CFG_BLOCKED 0x00000004 #define PHB4_CAPP_RECOVERY 0x00000008 +#define PHB4_CAPP_DISABLE 0x00000010 struct phb4 { unsigned int index; /* 0..5 index inside p9 */ From patchwork Tue Jan 8 09:59:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1021828 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43Ynq65sFrz9sMp for ; Tue, 8 Jan 2019 21:01:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43Ynq64YhtzDqPc for ; Tue, 8 Jan 2019 21:01:54 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43Ynmg25y8zDqRk for ; Tue, 8 Jan 2019 20:59:47 +1100 (AEDT) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x089x6c0083630 for ; Tue, 8 Jan 2019 04:59:45 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pvr6tdh5w-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 04:59:45 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 8 Jan 2019 09:59:42 -0000 Received: from b06cxnps3075.portsmouth.uk.ibm.com (9.149.109.195) by e06smtp01.uk.ibm.com (192.168.101.131) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 8 Jan 2019 09:59:40 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x089xcAB51904732 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Jan 2019 09:59:38 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AC48EAE04D; Tue, 8 Jan 2019 09:59:38 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F17B2AE045; Tue, 8 Jan 2019 09:59:36 +0000 (GMT) Received: from vajain21.in.ibm.com (unknown [9.109.223.28]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 8 Jan 2019 09:59:36 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith , Vasant Hegde Date: Tue, 8 Jan 2019 15:29:01 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190108095902.24718-1-vaibhav@linux.ibm.com> References: <20190108095902.24718-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19010809-4275-0000-0000-000002FBD672 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010809-4276-0000-0000-00003809E0E5 Message-Id: <20190108095902.24718-8-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-08_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901080082 Subject: [Skiboot] [PATCH v3 7/8] phb4/capp: Implement sequence to disable CAPP and enable fast-reset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We implement h/w sequence to disable CAPP in disable_capi_mode() and with it also enable fast-reset for CAPI mode in phb4_set_capi_mode(). Sequence to disable CAPP is executed in three phases. The first two phase is implemented in disable_capi_mode() where we reset the CAPP registers followed by PEC registers to their init values. The final third final phase is to reset the PHB CAPI Compare/Mask Register and is done in phb4_init_ioda3(). The reason to move the PHB reset to phb4_init_ioda3() is because by the time Opal PCI reset state machine reaches this function the PHB is already un-fenced and its configuration registers accessible via mmio. Reviewed-by: Andrew Donnellan Signed-off-by: Vaibhav Jain Reviewed-by: Christophe Lombard Reviewed-by: Frederic Barrat --- Change-log v3: Use the capp_xscom_write() instead of xscom_write(). Minor change of a branch condition [ Andrew ] v2: Instead of using the 'PHB4_CAPP_REG_OFFSET' macro use the 'struct capp->capp_xscom_offset' member. --- hw/phb4.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 64 insertions(+), 3 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 88b1a6fb..6b330793 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3218,7 +3218,67 @@ static void disable_capi_mode(struct phb4 *p) PHBINF(p, "CAPP: Disabling CAPI mode\n"); - /* Implement procedure to disable CAPP based on h/w sequence */ + /* First Phase Reset CAPP Registers */ + /* CAPP about to be disabled mark TLBI_FENCED and tlbi_psl_is_dead */ + capp_xscom_write(capp, CAPP_ERR_STATUS_CTRL, PPC_BIT(3) | PPC_BIT(4)); + + /* Flush SUE uOP1 Register */ + if (p->rev != PHB4_REV_NIMBUS_DD10) + capp_xscom_write(capp, FLUSH_SUE_UOP1, 0); + + /* Release DMA/STQ engines */ + capp_xscom_write(capp, APC_FSM_READ_MASK, 0ull); + capp_xscom_write(capp, XPT_FSM_RMM, 0ull); + + /* Disable snoop */ + capp_xscom_write(capp, SNOOP_CAPI_CONFIG, 0); + + /* Clear flush SUE state map register */ + capp_xscom_write(capp, FLUSH_SUE_STATE_MAP, 0); + + /* Disable epoch timer */ + capp_xscom_write(capp, EPOCH_RECOVERY_TIMERS_CTRL, 0); + + /* CAPP Transport Control Register */ + capp_xscom_write(capp, TRANSPORT_CONTROL, PPC_BIT(15)); + + /* Disable snooping */ + capp_xscom_write(capp, SNOOP_CONTROL, 0); + capp_xscom_write(capp, SNOOP_CAPI_CONFIG, 0); + + /* APC Master PB Control Register - disable examining cResps */ + capp_xscom_write(capp, APC_MASTER_PB_CTRL, 0); + + /* APC Master Config Register - de-select PHBs */ + xscom_write_mask(p->chip_id, capp->capp_xscom_offset + + APC_MASTER_CAPI_CTRL, 0, PPC_BITMASK(2, 3)); + + /* Clear all error registers */ + capp_xscom_write(capp, CAPP_ERR_RPT_CLR, 0); + capp_xscom_write(capp, CAPP_FIR, 0); + capp_xscom_write(capp, CAPP_FIR_ACTION0, 0); + capp_xscom_write(capp, CAPP_FIR_ACTION1, 0); + capp_xscom_write(capp, CAPP_FIR_MASK, 0); + + /* Second Phase Reset PEC/PHB Registers */ + + /* Reset the stack overrides if any */ + xscom_write(p->chip_id, p->pci_xscom + XPEC_PCI_PRDSTKOVR, 0); + xscom_write(p->chip_id, p->pe_xscom + + XPEC_NEST_READ_STACK_OVERRIDE, 0); + + /* PE Bus AIB Mode Bits. Disable Tracing. Leave HOL Blocking as it is */ + if (!(p->rev == PHB4_REV_NIMBUS_DD10) && p->index == CAPP1_PHB_INDEX) + xscom_write_mask(p->chip_id, + p->pci_xscom + XPEC_PCI_PBAIB_HW_CONFIG, 0, + PPC_BIT(30)); + + /* Reset for PCI to PB data movement */ + xscom_write_mask(p->chip_id, p->pe_xscom + XPEC_NEST_PBCQ_HW_CONFIG, + 0, XPEC_NEST_PBCQ_HW_CONFIG_PBINIT); + + /* Disable CAPP mode in PEC CAPP Control Register */ + xscom_write(p->chip_id, p->pe_xscom + XPEC_NEST_CAPP_CNTL, 0ull); } static int64_t phb4_creset(struct pci_slot *slot) @@ -4621,8 +4681,6 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, /* register notification on system shutdown */ opal_add_host_sync_notifier(&phb4_host_sync_reset, p); - /* Disable fast reboot for CAPP */ - disable_fast_reboot("CAPP being enabled"); } else { /* In case of an error mark the PHB detached */ capp->phb = NULL; @@ -4838,6 +4896,9 @@ static void phb4_init_ioda3(struct phb4 *p) /* Init_26 - CAPI Compare/Mask */ /* See enable_capi_mode() */ + /* if CAPP being disabled then reset CAPI Compare/Mask Register */ + if (p->flags & PHB4_CAPP_DISABLE) + out_be64(p->regs + PHB_CAPI_CMPM, 0); /* Init_27 - PCIE Outbound upper address */ out_be64(p->regs + PHB_M64_UPPER_BITS, 0); From patchwork Tue Jan 8 09:59:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1021829 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43Ynqh2bB2z9sN8 for ; Tue, 8 Jan 2019 21:02:24 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43Ynqg4fQSzDqRH for ; Tue, 8 Jan 2019 21:02:23 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43Ynmj4Gf0zDqPb for ; Tue, 8 Jan 2019 20:59:49 +1100 (AEDT) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x089x8P1119526 for ; Tue, 8 Jan 2019 04:59:47 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pvphban2e-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 04:59:47 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 8 Jan 2019 09:59:45 -0000 Received: from b06cxnps4075.portsmouth.uk.ibm.com (9.149.109.197) by e06smtp04.uk.ibm.com (192.168.101.134) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 8 Jan 2019 09:59:43 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x089xfdP41287818 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Jan 2019 09:59:41 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 90E63AE055; Tue, 8 Jan 2019 09:59:41 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0786AAE045; Tue, 8 Jan 2019 09:59:40 +0000 (GMT) Received: from vajain21.in.ibm.com (unknown [9.109.223.28]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 8 Jan 2019 09:59:39 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith , Vasant Hegde Date: Tue, 8 Jan 2019 15:29:02 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190108095902.24718-1-vaibhav@linux.ibm.com> References: <20190108095902.24718-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19010809-0016-0000-0000-00000241DE28 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010809-0017-0000-0000-0000329BF0D7 Message-Id: <20190108095902.24718-9-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-08_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901080082 Subject: [Skiboot] [PATCH v3 8/8] capp/phb4: Prevent HMI from getting triggered when disabling CAPP X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" While disabling CAPP an HMI gets triggered as soon as ETU is put in reset mode. This is caused as before we can disabled CAPP, it detects PHB link going down and triggers an HMI requesting Opal to perform CAPP recovery. This has an un-intended side effect of spamming the Opal logs with malfunction alert messages and may also confuse the user. To prevent this we mask the CAPP FIR error 'PHB Link Down' Bit(31) when we are disabling CAPP just before we put ETU in reset in phb4_creset(). Also now since bringing down the PHB link now wont trigger an HMI and CAPP recovery, hence we manually set the PHB4_CAPP_RECOVERY flag on the phb to force recovery during creset. Reviewed-by: Andrew Donnellan Signed-off-by: Vaibhav Jain Reviewed-by: Christophe Lombard Reviewed-by: Frederic Barrat --- Change-log v3: Fetch the pointer to 'struct capp' from struct phb4 instead of struct phb. v2: Use the member 'struct capp->capp_xscom_offset' to find the xscom register offset instead of 'PHB4_CAPP_REG_OFFSET'. --- hw/phb4.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/phb4.c b/hw/phb4.c index 6b330793..73b2c40d 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3284,6 +3284,7 @@ static void disable_capi_mode(struct phb4 *p) static int64_t phb4_creset(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); + struct capp *capp = p->capp; uint64_t pbcq_status, reg; /* Don't even try fixing a broken PHB */ @@ -3299,6 +3300,16 @@ static int64_t phb4_creset(struct pci_slot *slot) /* Clear error inject register, preventing recursive errors */ xscom_write(p->chip_id, p->pe_xscom + 0x2, 0x0); + /* Prevent HMI when PHB gets fenced as we are disabling CAPP */ + if (p->flags & PHB4_CAPP_DISABLE && + capp && capp->phb == slot->phb) { + /* Since no HMI, So set the recovery flag manually. */ + p->flags |= PHB4_CAPP_RECOVERY; + xscom_write_mask(p->chip_id, capp->capp_xscom_offset + + CAPP_FIR_MASK, + PPC_BIT(31), PPC_BIT(31)); + } + /* Force fence on the PHB to work around a non-existent PE */ if (!phb4_fenced(p)) xscom_write(p->chip_id, p->pe_stk_xscom + 0x2,