From patchwork Mon Jan 7 10:09:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 1021251 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="CNa/UFoG"; dkim=pass (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="nFe4zjw4"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YB4k4yZmz9sDP for ; Mon, 7 Jan 2019 21:11:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726795AbfAGKKS (ORCPT ); Mon, 7 Jan 2019 05:10:18 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55772 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726601AbfAGKKS (ORCPT ); Mon, 7 Jan 2019 05:10:18 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 20F52609D4; Mon, 7 Jan 2019 10:10:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1546855817; bh=9zw1nV97nLtoQKZBtBtEAT12fbWhim0zzQLOZHMoGyE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CNa/UFoGDQIcXvOqDupuB+7Y1AydjMXNVgLRhFsHiixUlRRtrCpISjVhZhdI877mQ dsP+palQ+v3KP19OK9j1MgRDsXuvN9UFNqejdWFiFAuM9PyKL7lqB9i7F00OO62qJw mYDvSiLU+nwVu141z1m6y0LBt4vG9zv5vUhkknag= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID, DKIM_SIGNED autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2999560954; Mon, 7 Jan 2019 10:10:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1546855815; bh=9zw1nV97nLtoQKZBtBtEAT12fbWhim0zzQLOZHMoGyE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nFe4zjw4tm8hBfSb7dP8FdP+ssYGjtCsurPfymkbl0HZXCsEkto7V1od2XOTRMQe9 Sux6zvhIDse83/29RKLWYbQCIG3TN0HpN4r8hRz0NfKI3VXFzwc99oxaR+d5eiTEMO +04aoBQAAAFKEo7UCNalRz2zALTnTfS06FJBYR38= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2999560954 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: andy.gross@linaro.org, robh@kernel.org, viresh.kumar@linaro.org, sboyd@kernel.org, ulf.hansson@linaro.org, collinsd@codeaurora.org, mka@chromium.org Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, henryc.chen@mediatek.com, Rajendra Nayak Subject: [PATCH v9 01/10] dt-bindings: opp: Introduce opp-level bindings Date: Mon, 7 Jan 2019 15:39:50 +0530 Message-Id: <20190107100959.14528-2-rnayak@codeaurora.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190107100959.14528-1-rnayak@codeaurora.org> References: <20190107100959.14528-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On some SoCs (especially from Qualcomm and MediaTek) an OPP node needs to describe an additional level/corner value that is then communicated to a remote microprocessor by the CPU, which then takes some actions (like adjusting voltage values across various rails) based on the value passed. Describe these bindings in the opp-level bindings document. Signed-off-by: Rajendra Nayak --- .../devicetree/bindings/opp/opp-level.txt | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/opp-level.txt diff --git a/Documentation/devicetree/bindings/opp/opp-level.txt b/Documentation/devicetree/bindings/opp/opp-level.txt new file mode 100644 index 000000000000..f9134ed08164 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/opp-level.txt @@ -0,0 +1,29 @@ +OPP level bindings to descibe OPP nodes with corner/level values + +OPP tables for devices on some SoCs, especially from Qualcomm and +MediaTek require an additional platform specific corner/level +value to be specified. +This value is passed on to a Power Manager by +the CPU, which then takes the necessary actions to set a voltage +rail to an appropriate voltage based on the value passed. + +The bindings are based on top of the operating-points-v2 bindings +described in Documentation/devicetree/bindings/opp/opp.txt, +with the exception that all of the properties are now optional, +including the opp-hz property. + +Additional properties are described below. + +* OPP Table Node + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2-level" + +* OPP Node + +Required properties: +- opp-level: On some SoC platforms an OPP node can describe a positive value +representing a corner/level that's communicated with a remote microprocessor +(usually called the power manager) which then translates it into a certain voltage on +a voltage rail. From patchwork Mon Jan 7 10:09:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 1021250 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="Vm7aBqHL"; dkim=pass (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="OAiOATMv"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YB4g70NWz9sDr for ; Mon, 7 Jan 2019 21:11:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726783AbfAGKKZ (ORCPT ); Mon, 7 Jan 2019 05:10:25 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:56092 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726873AbfAGKKY (ORCPT ); Mon, 7 Jan 2019 05:10:24 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2B30B60A37; Mon, 7 Jan 2019 10:10:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1546855823; bh=yQ4FheJC5BDW+Q/FeprIjkBhVrkPTT8oY993ejs2JKo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vm7aBqHLhuOmBOs46DTffiYatXV3dNdoeBe0CBvBdPY2VtCR1mjeyDMlFyWTjPgqN JMYUq/FxrWKkgYQOV/eC0BswfauN2moL2XImbrmV/6BZgGIIOwKDgZ0nDUr/HZU+hg 3tMVNIXs915a0eajMhmkFyuFkh3VwNAYI8vh+j9c= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID, DKIM_SIGNED autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CACD9609C6; Mon, 7 Jan 2019 10:10:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1546855819; bh=yQ4FheJC5BDW+Q/FeprIjkBhVrkPTT8oY993ejs2JKo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OAiOATMvvPn6f7dZ2IcO/WIz8oyExLcmjR2occX7TNd5Qnn1WFHIZWWqgNGHdsoLO Wb+S1q7A27dU0JOJI8C1k8PlIhmXe0A8KSuu7aADYxmDlythgixQkXuR7Uh8XOhe5o tFZD9Ueavizt3y9NbQHTMJ86UfhTcuAQkq22PwKk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CACD9609C6 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: andy.gross@linaro.org, robh@kernel.org, viresh.kumar@linaro.org, sboyd@kernel.org, ulf.hansson@linaro.org, collinsd@codeaurora.org, mka@chromium.org Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, henryc.chen@mediatek.com, Rajendra Nayak Subject: [PATCH v9 02/10] dt-bindings: power: Add qcom rpm power domain driver bindings Date: Mon, 7 Jan 2019 15:39:51 +0530 Message-Id: <20190107100959.14528-3-rnayak@codeaurora.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190107100959.14528-1-rnayak@codeaurora.org> References: <20190107100959.14528-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings to describe the rpm/rpmh power domains found on Qualcomm Technologies, Inc. SoCs. These power domains communicate a performance state to RPM/RPMh, which then translates it into corresponding voltage on a PMIC rail. Signed-off-by: Rajendra Nayak Signed-off-by: Viresh Kumar Reviewed-by: Ulf Hansson Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- .../devicetree/bindings/power/qcom,rpmpd.txt | 145 ++++++++++++++++++ include/dt-bindings/power/qcom-rpmpd.h | 39 +++++ 2 files changed, 184 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/qcom,rpmpd.txt create mode 100644 include/dt-bindings/power/qcom-rpmpd.h diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt new file mode 100644 index 000000000000..2f0764298d86 --- /dev/null +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt @@ -0,0 +1,145 @@ +Qualcomm RPM/RPMh Power domains + +For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh +which then translates it into a corresponding voltage on a rail + +Required Properties: + - compatible: Should be one of the following + * qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC + * qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC + - #power-domain-cells: number of cells in Power domain specifier + must be 1. + - operating-points-v2: Phandle to the OPP table for the Power domain. + Refer to Documentation/devicetree/bindings/power/power_domain.txt + and Documentation/devicetree/bindings/opp/opp-level.txt for more details + +Refer to for the level values for +various OPPs for different platforms as well as Power domain indexes + +Example: rpmh power domain controller and OPP table + +#include + +opp-level values specified in the OPP tables for RPMh power domains +should use the RPMH_REGULATOR_LEVEL_* constants from + + + rpmhpd: power-controller { + compatible = "qcom,sdm845-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2-level"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + +Example: rpm power domain controller and OPP table + + rpmpd: power-controller { + compatible = "qcom,msm8996-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2-level"; + + rpmpd_opp_low: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_ret: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_normal: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_high: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + +Example: Client/Consumer device using OPP table + + leaky-device0@12350000 { + compatible = "foo,i-leak-current"; + reg = <0x12350000 0x1000>; + power-domains = <&rpmhpd SDM845_MX>; + operating-points-v2 = <&leaky_opp_table>; + }; + + + leaky_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp1 { + opp-hz = /bits/ 64 <144000>; + required-opps = <&rpmhpd_opp_low>; + }; + + opp2 { + opp-hz = /bits/ 64 <400000>; + required-opps = <&rpmhpd_opp_ret>; + }; + + opp3 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp4 { + opp-hz = /bits/ 64 <25000000>; + required-opps = <&rpmpd_opp_normal>; + }; + }; diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h new file mode 100644 index 000000000000..87d9c6611682 --- /dev/null +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ + +#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H +#define _DT_BINDINGS_POWER_QCOM_RPMPD_H + +/* SDM845 Power Domain Indexes */ +#define SDM845_EBI 0 +#define SDM845_MX 1 +#define SDM845_MX_AO 2 +#define SDM845_CX 3 +#define SDM845_CX_AO 4 +#define SDM845_LMX 5 +#define SDM845_LCX 6 +#define SDM845_GFX 7 +#define SDM845_MSS 8 + +/* SDM845 Power Domain performance levels */ +#define RPMH_REGULATOR_LEVEL_RETENTION 16 +#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_SVS 128 +#define RPMH_REGULATOR_LEVEL_SVS_L1 192 +#define RPMH_REGULATOR_LEVEL_NOM 256 +#define RPMH_REGULATOR_LEVEL_NOM_L1 320 +#define RPMH_REGULATOR_LEVEL_NOM_L2 336 +#define RPMH_REGULATOR_LEVEL_TURBO 384 +#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 + +/* MSM8996 Power Domain Indexes */ +#define MSM8996_VDDCX 0 +#define MSM8996_VDDCX_AO 1 +#define MSM8996_VDDCX_VFC 2 +#define MSM8996_VDDMX 3 +#define MSM8996_VDDMX_AO 4 +#define MSM8996_VDDSSCX 5 +#define MSM8996_VDDSSCX_VFC 6 + +#endif