From patchwork Thu Aug 31 13:57:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 808257 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xjkV53Hzcz9sPm for ; Thu, 31 Aug 2017 23:58:05 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3183DC21E4A; Thu, 31 Aug 2017 13:57:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C51B8C21DB5; Thu, 31 Aug 2017 13:57:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 64A29C21DB5; Thu, 31 Aug 2017 13:57:55 +0000 (UTC) Received: from wens.csie.org (mirror2.csie.ntu.edu.tw [140.112.30.76]) by lists.denx.de (Postfix) with ESMTPS id 9645AC21D99 for ; Thu, 31 Aug 2017 13:57:54 +0000 (UTC) Received: by wens.csie.org (Postfix, from userid 1000) id 42A255FB68; Thu, 31 Aug 2017 21:57:49 +0800 (CST) From: Chen-Yu Tsai To: u-boot@lists.denx.de Date: Thu, 31 Aug 2017 21:57:48 +0800 Message-Id: <20170831135748.32498-1-wens@csie.org> X-Mailer: git-send-email 2.14.1 Cc: Jagan Teki , Maxime Ripard Subject: [U-Boot] [PATCH] mmc: sunxi: Only update timing mode bit when enabling new timing mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When enabling the new mmc timing mode, we inadvertently clear all the remaining bits in the new timing mode register. The bits cleared include a default phase delay on the output clock. The BSP kernel states that the default values are supposed to be used. Clearing them results in decreased performance or transfer errors on some boards. Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode") Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index a76e763bfd4f..4edb4be46c81 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -167,7 +167,7 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) if (new_mode) { #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE val = CCM_MMC_CTRL_MODE_SEL_NEW; - writel(SUNXI_MMC_NTSR_MODE_SEL_NEW, &priv->reg->ntsr); + setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif } else { val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |