From patchwork Sat Dec 15 06:05:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1013839 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="JZTR2yU6"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43GxkM2xDTz9s5c for ; Sat, 15 Dec 2018 17:06:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D55B6C21FAF; Sat, 15 Dec 2018 06:05:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E0A7CC21F99; Sat, 15 Dec 2018 06:05:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3F109C220CE; Sat, 15 Dec 2018 06:05:41 +0000 (UTC) Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) by lists.denx.de (Postfix) with ESMTPS id 5A049C21F75 for ; Sat, 15 Dec 2018 06:05:36 +0000 (UTC) Received: by mail-pl1-f193.google.com with SMTP id y1so3684714plp.9 for ; Fri, 14 Dec 2018 22:05:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+CLzK4XICtNLX5OLcqb+zdKa00hXygFciDHNom+rz+U=; b=JZTR2yU6VQ6eakbLub6hQCKn7OD+XpR/bflUKDYlTnwgvlZWGmOdjCTvAJKvEh//Lf OABkNwrQ+8bi7kR6OCuFjLmMKDtiES6eBJGyfHgJrTvjZCu2afKYMr068OgN+UZVhGyI Na9i9DCj2FBUsciplz1mPMGpX2OWJTnMk9k6HR5ga4XnO9NqziAfQ1E2o8x59cYJQmGb nDg+WnuzGXu0UEG07fBGv5xSg3r5BObJ9pieGAJRQQ1b05F3jHxU0NmUL2JKPDZ8wxH6 /HvMqfZ2OG5j+NC5af3Mj1oYH1EviGBv+C+SvaZ14vyCTIA88YDfzQft5R5MDpLRliPJ h7hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+CLzK4XICtNLX5OLcqb+zdKa00hXygFciDHNom+rz+U=; b=pYPVp9lLmmIKPbOlzzC31xvGJEKFKhzwEGuJRef6uJ7goDSfr63E2M5SZqAh7CEplm dtPsjzReOPqId7Tm0mNBFdVQlPqod4wmjD3wiF0B34NPqnsj7QF2aA/z4Ql3zA7pillD 3M/0T+MlPDAoRLAPMmSv6n4zu9XO1PyqqJ4351WEqwZLFhfmBrhxRyO2GCHW+l4Dwh5z RhIJ/Pr2OVa+hIuN8u9rAfbojHHl4p97uLYOdxb7tVewDeLEIEwFiuMJXDoNAPAxNV7/ kwkRXUtYM8G8BlGzDxCUjftlDCfb6ztvbtl79Lwsd4jXCbejTKRyVPOgecli8aTzZuU7 QGmA== X-Gm-Message-State: AA+aEWZhexqHyglrdNN256Hp3NkAd5En1VC7aTmNYiMFyDwHg7lrR/pB IJ4OzZjwrsBdwxytnITz+Eae4g== X-Google-Smtp-Source: AFSGD/XtX8COQ/CtdaE26TfiSXJ3hd/3+CXXcrmnikImME8Q1lj5MnILbMArGEaEe98exInJV4F+8w== X-Received: by 2002:a17:902:9887:: with SMTP id s7mr5307080plp.199.1544853934716; Fri, 14 Dec 2018 22:05:34 -0800 (PST) Received: from localhost.localdomain ([106.51.16.228]) by smtp.gmail.com with ESMTPSA id a4sm7153647pgv.70.2018.12.14.22.05.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Dec 2018 22:05:34 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Sat, 15 Dec 2018 11:35:15 +0530 Message-Id: <20181215060516.61933-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181215060516.61933-1-anup@brainfault.org> References: <20181215060516.61933-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v3 1/2] drivers: serial: Add SiFive UART driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds SiFive UART driver. The driver is 100% DM driver and it determines input clock using clk framework. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/serial/Kconfig | 13 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_sifive.c | 215 +++++++++++++++++++++++++++++++++ 3 files changed, 229 insertions(+) create mode 100644 drivers/serial/serial_sifive.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6252dd8c4b..b7ff2960ab 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -343,6 +343,13 @@ config DEBUG_UART_SANDBOX start up driver model. The driver will be available until the real driver model serial is running. +config DEBUG_UART_SIFIVE + bool "SiFive UART" + help + Select this to enable a debug UART using the serial_sifive driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_STM32 bool "STMicroelectronics STM32" depends on STM32_SERIAL @@ -679,6 +686,12 @@ config PXA_SERIAL If you have a machine based on a Marvell XScale PXA2xx CPU you can enable its onboard serial ports by enabling this option. +config SIFIVE_SERIAL + bool "SiFive UART support" + depends on DM_SERIAL + help + This driver supports the SiFive UART. If unsure say N. + config STI_ASC_SERIAL bool "STMicroelectronics on-chip UART" depends on DM_SERIAL && ARCH_STI diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 2f8d065a4c..06ee30697d 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o +obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c new file mode 100644 index 0000000000..341728a690 --- /dev/null +++ b/drivers/serial/serial_sifive.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Anup Patel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_TXFIFO_FULL 0x80000000 +#define UART_RXFIFO_EMPTY 0x80000000 +#define UART_RXFIFO_DATA 0x000000ff +#define UART_TXCTRL_TXEN 0x1 +#define UART_RXCTRL_RXEN 0x1 + +struct uart_sifive { + u32 txfifo; + u32 rxfifo; + u32 txctrl; + u32 rxctrl; + u32 ie; + u32 ip; + u32 div; +}; + +struct sifive_uart_platdata { + unsigned int clock; + int saved_input_char; + struct uart_sifive *regs; +}; + +/* Set up the baud rate in gd struct */ +static void _sifive_serial_setbrg(struct uart_sifive *regs, + unsigned long clock, unsigned long baud) +{ + writel((u32)((clock / baud) - 1), ®s->div); +} + +static void _sifive_serial_init(struct uart_sifive *regs) +{ + writel(UART_TXCTRL_TXEN, ®s->txctrl); + writel(UART_RXCTRL_RXEN, ®s->rxctrl); + writel(0, ®s->ie); +} + +static int _sifive_serial_putc(struct uart_sifive *regs, const char c) +{ + if (readl(®s->txfifo) & UART_TXFIFO_FULL) + return -EAGAIN; + + writel(c, ®s->txfifo); + + return 0; +} + +static int _sifive_serial_getc(struct uart_sifive *regs) +{ + int ch = readl(®s->rxfifo); + + if (ch & UART_RXFIFO_EMPTY) + return -EAGAIN; + ch &= UART_RXFIFO_DATA; + + return (!ch) ? -EAGAIN : ch; +} + +static int sifive_serial_setbrg(struct udevice *dev, int baudrate) +{ + int err; + struct clk clk; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + platdata->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("SiFive UART failed to get clock\n"); + return err; + } + + if (!platdata->clock) + platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0); + if (!platdata->clock) { + debug("SiFive UART clock not defined\n"); + return -EINVAL; + } + + _sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate); + + return 0; +} + +static int sifive_serial_probe(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + /* No need to reinitialize the UART after relocation */ + if (gd->flags & GD_FLG_RELOC) + return 0; + + platdata->saved_input_char = 0; + _sifive_serial_init(platdata->regs); + + return 0; +} + +static int sifive_serial_getc(struct udevice *dev) +{ + int c; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_sifive *regs = platdata->regs; + + if (platdata->saved_input_char > 0) { + c = platdata->saved_input_char; + platdata->saved_input_char = 0; + return c; + } + + while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ; + + return c; +} + +static int sifive_serial_putc(struct udevice *dev, const char ch) +{ + int rc; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ; + + return rc; +} + +static int sifive_serial_pending(struct udevice *dev, bool input) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_sifive *regs = platdata->regs; + + if (input) { + if (platdata->saved_input_char > 0) + return 1; + platdata->saved_input_char = _sifive_serial_getc(regs); + return (platdata->saved_input_char > 0) ? 1 : 0; + } else { + return !!(readl(®s->txfifo) & UART_TXFIFO_FULL); + } +} + +static int sifive_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + platdata->regs = (struct uart_sifive *)dev_read_addr(dev); + if (IS_ERR(platdata->regs)) + return PTR_ERR(platdata->regs); + + return 0; +} + +static const struct dm_serial_ops sifive_serial_ops = { + .putc = sifive_serial_putc, + .getc = sifive_serial_getc, + .pending = sifive_serial_pending, + .setbrg = sifive_serial_setbrg, +}; + +static const struct udevice_id sifive_serial_ids[] = { + { .compatible = "sifive,uart0" }, + { } +}; + +U_BOOT_DRIVER(serial_sifive) = { + .name = "serial_sifive", + .id = UCLASS_SERIAL, + .of_match = sifive_serial_ids, + .ofdata_to_platdata = sifive_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata), + .probe = sifive_serial_probe, + .ops = &sifive_serial_ops, +}; + +#ifdef CONFIG_DEBUG_UART_SIFIVE +static inline void _debug_uart_init(void) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); + _sifive_serial_init(regs); +} + +static inline void _debug_uart_putc(int ch) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + while (_sifive_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); +} + +DEBUG_UART_FUNCS + +#endif From patchwork Sat Dec 15 06:05:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1013840 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="blXugh1k"; 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Fri, 14 Dec 2018 22:05:40 -0800 (PST) Received: from localhost.localdomain ([106.51.16.228]) by smtp.gmail.com with ESMTPSA id a4sm7153647pgv.70.2018.12.14.22.05.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Dec 2018 22:05:40 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Sat, 15 Dec 2018 11:35:16 +0530 Message-Id: <20181215060516.61933-3-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181215060516.61933-1-anup@brainfault.org> References: <20181215060516.61933-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v3 2/2] riscv: qemu: Imply SIFIVE_SERIAL for emulation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch enables SiFive UART driver for QEMU RISC-V emulation by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index ed005e5678..0d865acf10 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -33,5 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FAT imply BOARD_LATE_INIT imply OF_BOARD_SETUP + imply SIFIVE_SERIAL endif