From patchwork Thu Dec 13 23:14:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1013203 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="qGqNTORO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43G8fQ6VHrz9sD9 for ; Fri, 14 Dec 2018 10:15:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728021AbeLMXOx (ORCPT ); Thu, 13 Dec 2018 18:14:53 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:15458 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726254AbeLMXOx (ORCPT ); Thu, 13 Dec 2018 18:14:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1544742896; x=1576278896; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Dw7BVJruXEjQ+4ypD9yLQOYA/HM5jvLkotJAMWN215w=; b=qGqNTOROOrqNT+dbRTCp/yyxyOfUcYWBaGQvB6THSnHW9JXJeH+r67Mq lqf7Nb+KhBTMlQHIs2Q3NceRRvywT3vK3Svb/aJNMgEP1TSWDUwhRY5Zj 1Qco2D7XSTIZcgnrjW20gZIN9/V1BnrHysf3KpAN16np2TMA7TBUbGz5M 5qB36z6Mda/acCdFIi2wP3m3MvGMXIoP7ZZ+jQt9gzWM4VsPrBxsOoSog rM1tg762/9PfMH5D2M9Kw5Ubu428+tc+A3DTBZoE3i8QpygTHT49q3JwI d4jOxstHgYa3UN10JLgu94YmIDriZz/xwvhKURg1uqRevjlMgXGqEJD4c g==; X-IronPort-AV: E=Sophos;i="5.56,350,1539619200"; d="scan'208";a="194445534" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 14 Dec 2018 07:14:55 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 13 Dec 2018 14:57:20 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Dec 2018 15:14:53 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Palmer Dabbelt , Christoph Hellwig , Atish Patra , Albert Ou , Daniel Lezcano , devicetree@vger.kernel.org, Dmitriy Cherkasov , linux-riscv@lists.infradead.org, Mark Rutland , Rob Herring , Thomas Gleixner , Anup Patel , Damien Le Moal , Christoph Hellwig Subject: [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency Date: Thu, 13 Dec 2018 15:14:26 -0800 Message-Id: <1544742869-19980-2-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> References: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Palmer Dabbelt In RISC-V systems, timebase-frequency is per cpu instead of one instance for entire SOC as there is a individual timer per each CPU. Fix the DT binding accordingly. Signed-off-by: Palmer Dabbelt Signed-off-by: Christoph Hellwig [Atish: Update the commit text] Signed-off-by: Atish Patra Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af..b0b038d6 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -93,9 +93,9 @@ Linux is allowed to run on. cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <1000000>; cpu@0 { clock-frequency = <1600000000>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; @@ -113,6 +113,7 @@ Linux is allowed to run on. }; cpu@1 { clock-frequency = <1600000000>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart This device tree matches the Spike ISA golden model as run with `spike -p1`. cpus { + timebase-frequency = <1000000>; cpu@0 { device_type = "cpu"; reg = <0x00000000>;