From patchwork Tue Dec 11 15:02:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1011127 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="mfDUp2kt"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DjrT4xGZz9s5c for ; Wed, 12 Dec 2018 02:03:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5640FC225A6; Tue, 11 Dec 2018 15:03:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 44CC8C225AA; Tue, 11 Dec 2018 15:02:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 22BAAC225C7; Tue, 11 Dec 2018 15:02:48 +0000 (UTC) Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) by lists.denx.de (Postfix) with ESMTPS id 39C4EC225AD for ; Tue, 11 Dec 2018 15:02:44 +0000 (UTC) Received: by mail-pl1-f193.google.com with SMTP id t13so7026514ply.13 for ; Tue, 11 Dec 2018 07:02:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zopB92zLyyWlp0SDwluxiyOQSw5zmcIsDgjxcxAlcSw=; b=mfDUp2ktU86zsS1ckL7Jma/YxJjCNh6piPEg0/yHOD2f/PQcp3RqRv8SpvcjDg78AX fIv8ovtI2rBtDOzby2mdpmJ4755tZXya3VgsM7tqoWIQ0x7VQWrHoKleVNeVKlv2hd6r 7uvFR+Yo1004ubJeSOZaphw27QEkLJ5sdaIzFgU7DaxNQDP6BuazWB2muebcqzs30qQY gMQhB+/cKDOgFDnGHHy2g4f3k1YkDkk6a/Hbp04gsOp3kUqDNrBX6Mq8oJDTrEAyjz83 ChDaL2FuA12inJIJ0fOHam5B7xPIsh4JZUxbYi5qyl6twAcqnYkjaRTD6+TlinA8AyCh TJiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zopB92zLyyWlp0SDwluxiyOQSw5zmcIsDgjxcxAlcSw=; b=O41cZkaPF1cfHaPLrMM66fpG0SMAyOyW/pSkGLtWeEuFPNciNQ9jdvkqsuhZg4UbNC S544knSkqQHOaNo8ZISvayZsr/3k6aH+DxYFu0sCDoIRAQ+oIou0QXhZ/QQFZ0JrDjbs Whxn7RFi+a2chumPQ8vgrGD9YYSPDyTWqcCMp2uHuB4YtNJ9RDMqbT9CJH0+2g9h+TOU nXXIlVqPjOS6DKguxXPDtfEL51Kyiswej7XJBKcOolQn3z/Y58/uqxQuEG8Nt8RACRIo HX3OGL71wI6sameQ78NoLw9R1RDL7FxQU0uw+k0wey9q/pqY5GVyXgcXmd9WVLdxzKFG O1sQ== X-Gm-Message-State: AA+aEWY630GGRIhqvgi7XlR28vn1zVDtz5Twweyf+WK2f+cXTaLLyphf sUCxFXqUvjuuZRWHfOGFK3di+w== X-Google-Smtp-Source: AFSGD/WcAw8VPvpqHx54a1L77ToALknr4rgOXAJiiaiDWsW+NYk8vfvv/E9gBE89NWiB/zjropSMmA== X-Received: by 2002:a17:902:bd4a:: with SMTP id b10mr16421860plx.232.1544540562553; Tue, 11 Dec 2018 07:02:42 -0800 (PST) Received: from localhost.localdomain ([106.51.21.244]) by smtp.gmail.com with ESMTPSA id m20sm15317063pgv.93.2018.12.11.07.02.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:41 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Tue, 11 Dec 2018 20:32:20 +0530 Message-Id: <20181211150221.62514-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181211150221.62514-1-anup@brainfault.org> References: <20181211150221.62514-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v2 1/2] drivers: serial: Add SiFive UART driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds SiFive UART driver. The driver is 100% DM driver and it determines input clock using clk framework. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/serial/Kconfig | 13 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_sifive.c | 191 +++++++++++++++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 drivers/serial/serial_sifive.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 3bcc61e731..30f7e00557 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -343,6 +343,13 @@ config DEBUG_UART_SANDBOX start up driver model. The driver will be available until the real driver model serial is running. +config DEBUG_UART_SIFIVE + bool "SiFive UART" + help + Select this to enable a debug UART using the serial_sifive driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_STM32 bool "STMicroelectronics STM32" depends on STM32_SERIAL @@ -685,6 +692,12 @@ config PXA_SERIAL If you have a machine based on a Marvell XScale PXA2xx CPU you can enable its onboard serial ports by enabling this option. +config SIFIVE_SERIAL + bool "SiFive UART support" + depends on DM_SERIAL + help + This driver supports the SiFive UART. If unsure say N. + config STI_ASC_SERIAL bool "STMicroelectronics on-chip UART" depends on DM_SERIAL && ARCH_STI diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index b6377b1076..b6781535a8 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o +obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c new file mode 100644 index 0000000000..252f0921ae --- /dev/null +++ b/drivers/serial/serial_sifive.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Anup Patel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_TXFIFO_FULL 0x80000000 +#define UART_RXFIFO_EMPTY 0x80000000 +#define UART_RXFIFO_DATA 0x000000ff +#define UART_TXCTRL_TXEN 0x1 +#define UART_RXCTRL_RXEN 0x1 + +struct uart_sifive { + u32 txfifo; + u32 rxfifo; + u32 txctrl; + u32 rxctrl; + u32 ie; + u32 ip; + u32 div; +}; + +struct sifive_uart_platdata { + unsigned int clock; + struct uart_sifive *regs; +}; + +/* Set up the baud rate in gd struct */ +static void _sifive_serial_setbrg(struct uart_sifive *regs, + unsigned long clock, unsigned long baud) +{ + writel((u32)((clock / baud) - 1), ®s->div); +} + +static void _sifive_serial_init(struct uart_sifive *regs) +{ + writel(UART_TXCTRL_TXEN, ®s->txctrl); + writel(UART_RXCTRL_RXEN, ®s->rxctrl); + writel(0, ®s->ie); +} + +static int _sifive_serial_putc(struct uart_sifive *regs, const char c) +{ + if (readl(®s->txfifo) & UART_TXFIFO_FULL) + return -EAGAIN; + + writel(c, ®s->txfifo); + + return 0; +} + +static int _sifive_serial_getc(struct uart_sifive *regs) +{ + int ch = readl(®s->rxfifo); + + if (ch & UART_RXFIFO_EMPTY) + return -EAGAIN; + ch &= UART_RXFIFO_DATA; + + return (!ch) ? -EAGAIN : ch; +} + +static int sifive_serial_setbrg(struct udevice *dev, int baudrate) +{ + int err; + struct clk clk; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + platdata->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("SiFive UART failed to get clock\n"); + return err; + } + + if (!platdata->clock) + platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0); + if (!platdata->clock) { + debug("SiFive UART clock not defined\n"); + return -EINVAL; + } + + _sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate); + + return 0; +} + +static int sifive_serial_probe(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + /* No need to reinitialize the UART after relocation */ + if (gd->flags & GD_FLG_RELOC) + return 0; + + _sifive_serial_init(platdata->regs); + + return 0; +} + +static int sifive_serial_getc(struct udevice *dev) +{ + int c; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_sifive *regs = platdata->regs; + + while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ; + + return c; +} + +static int sifive_serial_putc(struct udevice *dev, const char ch) +{ + int rc; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ; + + return rc; +} + +static int sifive_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + platdata->regs = (struct uart_sifive *)dev_read_addr(dev); + if (IS_ERR(platdata->regs)) + return PTR_ERR(platdata->regs); + + return 0; +} + +static const struct dm_serial_ops sifive_serial_ops = { + .putc = sifive_serial_putc, + .getc = sifive_serial_getc, + .setbrg = sifive_serial_setbrg, +}; + +static const struct udevice_id sifive_serial_ids[] = { + { .compatible = "sifive,uart0" }, + { } +}; + +U_BOOT_DRIVER(serial_sifive) = { + .name = "serial_sifive", + .id = UCLASS_SERIAL, + .of_match = sifive_serial_ids, + .ofdata_to_platdata = sifive_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata), + .probe = sifive_serial_probe, + .ops = &sifive_serial_ops, +}; + +#ifdef CONFIG_DEBUG_UART_SIFIVE +static inline void _debug_uart_init(void) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); + _sifive_serial_init(regs); +} + +static inline void _debug_uart_putc(int ch) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + while (_sifive_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); +} + +DEBUG_UART_FUNCS + +#endif From patchwork Tue Dec 11 15:02:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1011128 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="Ks/qQNpo"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43Djrb2DKMz9s5c for ; Wed, 12 Dec 2018 02:03:59 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C58A8C22596; Tue, 11 Dec 2018 15:03:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4E993C2258B; Tue, 11 Dec 2018 15:03:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C3F0EC225B9; Tue, 11 Dec 2018 15:02:52 +0000 (UTC) Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) by lists.denx.de (Postfix) with ESMTPS id 6D11BC22591 for ; Tue, 11 Dec 2018 15:02:48 +0000 (UTC) Received: by mail-pl1-f193.google.com with SMTP id p8so7053677plo.2 for ; Tue, 11 Dec 2018 07:02:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EgU1bTz4DdtA/ozvDooQtCga58gXzWuF646BsDDuar4=; b=Ks/qQNpoe8x/HsiHrUI/7yptNL1w+bw5255vrjLS5OysSm2VqxN6aIy+EXJyumMk/+ E2SVnPqzENNk2lpw/nUdRygZRrdSKSX/eiFn28uwS6nDPMo1pKeFR7HobOUEWCGby2LS 8lzINn6Xeah7uJoTXTWXiRio3GA/81rxni2gYe2ywzJJws3Tg+PoJvPMbtSHvqZI8YQc hMr+1l0uBzjRofnAvT5wNBHeA7wts6480gSP2fn5p42KBsJo/NuvM7CXT44CvOyserLB qCADZ/zahuHSHwJeum2fh8W5TLbfWw5GfRvqzmVUu1aDPhnfz0cmxl9BwEIuRm5OOCnx X0FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EgU1bTz4DdtA/ozvDooQtCga58gXzWuF646BsDDuar4=; b=N+I5Tgy7BUhjNVuYjHygJNpFTpLrLaln6xwmQYNETJxehC7nEz2EJ5rpYJ5My5A0P5 SwnZEtBcY3xWeyOvyh/jkctoxkYM15TQIoaOI7PdjRtgp1Bmzt7+XHx711q9WAv8Zi4h YcWTwsJ5B8omskhvbUDx6MQXfGBjg4pj4nidVASXUUUjibyzGoTuqEHzs0n75XsfUxZn 7WRLFD/5GxDMuDS+xnzx1Q87HPxTkquJMXd7NjIMR0kPo/K1s2x4rTIIB7urF3fJxMUd TVYiLhiI8SsYVVHG55ZHM1ZiEefwkjpUY8ArWXwRMdPJpFbQkrpRkdmDQ3IKfBrzsNiZ qHSQ== X-Gm-Message-State: AA+aEWaykBQItGb0/J6xRFEoyL0Y1ZcuC1lk3Qj49r9B3w8GomrY3yta a9IGl96MHewa3JazD/TWR5pHFQ== X-Google-Smtp-Source: AFSGD/Xi1NE2u8aABf5eVFfSQvc5NKBGLClB6IX0Ved1dq1HOMWGVldw9IObkmMxdGIyv13blfABFA== X-Received: by 2002:a17:902:7d90:: with SMTP id a16mr15619940plm.249.1544540566848; Tue, 11 Dec 2018 07:02:46 -0800 (PST) Received: from localhost.localdomain ([106.51.21.244]) by smtp.gmail.com with ESMTPSA id m20sm15317063pgv.93.2018.12.11.07.02.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:46 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Tue, 11 Dec 2018 20:32:21 +0530 Message-Id: <20181211150221.62514-3-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181211150221.62514-1-anup@brainfault.org> References: <20181211150221.62514-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v2 2/2] riscv: qemu: Imply SIFIVE_SERIAL for emulation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch enables SiFive UART driver for QEMU RISC-V emulation by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 56bb5337d4..436db01a53 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -32,5 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FAT imply BOARD_LATE_INIT imply OF_BOARD_SETUP + imply SIFIVE_SERIAL endif